From: Valery Pykhtin <valery.pykhtin@gmail.com>
Date: Thu, 27 Oct 2022 06:55:16 +0000 (+0200)
Subject: [AMDGPU] Scheduler: fix RP calculation for a MBB with one successor
X-Git-Tag: upstream/17.0.6~15526
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a999669982d0cedacbb7371c96fce95682d582e1;p=platform%2Fupstream%2Fllvm.git

[AMDGPU] Scheduler: fix RP calculation for a MBB with one successor

We reuse live registers after tracking one MBB as live-ins to the successor MBB
if the successor is only one but we don't check if the successor has other predecessors.

`A   B`
` \ /`
`  C`

A and B have one successor but C has live-ins defined by A and B and therefore should be
initialized using LIS.

This fixes 83 lit tests out if 420 with EXPENSIVE_CHECK enabled.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D136918
---

diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index f9c58e8..7f7d6e5 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -511,11 +511,19 @@ void GCNScheduleDAGMILive::computeBlockPressure(unsigned RegionIdx,
   // If the block has the only successor then live-ins of that successor are
   // live-outs of the current block. We can reuse calculated live set if the
   // successor will be sent to scheduling past current block.
+
+  // However, due to the bug in LiveInterval analysis it may happen that two
+  // predecessors of the same successor block have different lane bitmasks for
+  // a live-out register. Workaround that by sticking to one-to-one relationship
+  // i.e. one predecessor with one successor block.
   const MachineBasicBlock *OnlySucc = nullptr;
-  if (MBB->succ_size() == 1 && !(*MBB->succ_begin())->empty()) {
-    SlotIndexes *Ind = LIS->getSlotIndexes();
-    if (Ind->getMBBStartIdx(MBB) < Ind->getMBBStartIdx(*MBB->succ_begin()))
-      OnlySucc = *MBB->succ_begin();
+  if (MBB->succ_size() == 1) {
+    auto *Candidate = *MBB->succ_begin();
+    if (!Candidate->empty() && Candidate->pred_size() == 1) {
+      SlotIndexes *Ind = LIS->getSlotIndexes();
+      if (Ind->getMBBStartIdx(MBB) < Ind->getMBBStartIdx(Candidate))
+        OnlySucc = Candidate;
+    }
   }
 
   // Scheduler sends regions from the end of the block upwards.