From: Laurentiu Tudor Date: Wed, 12 Dec 2018 11:45:51 +0000 (+0200) Subject: armv8: fsl-layerscape: properly configure qdma ICID X-Git-Tag: v2019.04-rc1~37^2~7 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a954f6fe70277a5d828937a5702fe8fec07f0d6e;p=platform%2Fkernel%2Fu-boot.git armv8: fsl-layerscape: properly configure qdma ICID The ICIDs for the qdma device are not configured through SCFG but through some registers found in the actual device register block. Signed-off-by: Laurentiu Tudor Reviewed-by: York Sun --- diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index a3f473f..f375fe7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -55,7 +55,11 @@ void fdt_fixup_icid(void *blob); CONFIG_SYS_FSL_ESDHC_ADDR) #define SET_QDMA_ICID(compat, streamid) \ - SET_SCFG_ICID(compat, streamid, dma_icid,\ + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ + QDMA_BASE_ADDR), \ + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ QDMA_BASE_ADDR) #define SET_EDMA_ICID(streamid) \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 4d0f16f..b4b7c34 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -94,6 +94,7 @@ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) +#define QMAN_CQSIDR_REG 0x20a80 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL