From: Rob Clark Date: Tue, 6 Dec 2016 20:52:28 +0000 (-0500) Subject: freedreno/a5xx: fix draw packet size with index buffer X-Git-Tag: upstream/17.1.0~4068 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a9383ae6d6eb71d30433b0346367af63bc979d34;p=platform%2Fupstream%2Fmesa.git freedreno/a5xx: fix draw packet size with index buffer gpuaddr of idx buffer is now two dwords (64b). Signed-off-by: Rob Clark --- diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h index 677bedf..8ce70d3 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h +++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h @@ -53,7 +53,7 @@ fd5_draw(struct fd_batch *batch, struct fd_ringbuffer *ring, */ emit_marker5(ring, 7); - OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 6 : 3); + OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 7 : 3); if (vismode == USE_VISIBILITY) { /* leave vis mode blank for now, it will be patched up when * we know if we are binning or not