From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Wed, 19 Apr 2023 13:09:40 +0000 (+0200)
Subject: Merge tag 'cacheinfo-updates-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git... 
X-Git-Tag: v6.6.17~5001^2~5
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a7b3a470fdea9f4a7daa5ae446c4e27c65f00aac;p=platform%2Fkernel%2Flinux-rpi.git

Merge tag 'cacheinfo-updates-6.4' of git://git./linux/kernel/git/sudeep.holla/linux into driver-core-next

Sudeep writes:

cacheinfo and arch_topology updates for v6.4

The cache information can be extracted from either a Device Tree(DT),
the PPTT ACPI table, or arch registers (clidr_el1 for arm64).

When the DT is used but no cache properties are advertised, the current
code doesn't correctly fallback to using arch information. The changes
fixes the same and also assuse the that L1 data/instruction caches
are private and L2/higher caches are shared when the cache information
is missing in DT/ACPI and is derived form clidr_el1/arch registers.

Currently the cacheinfo is built from the primary CPU prior to secondary
CPUs boot, if the DT/ACPI description contains cache information.
However, if not present, it still reverts to the old behavior, which
allocates the cacheinfo memory on each secondary CPUs which causes
RT kernels to triggers a "BUG: sleeping function called from invalid
context".

The changes here attempts to enable automatic detection for RT kernels
when no DT/ACPI cache information is available, by pre-allocating
cacheinfo memory on the primary CPU.

* tag 'cacheinfo-updates-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  cacheinfo: Add use_arch[|_cache]_info field/function
  arch_topology: Remove early cacheinfo error message if -ENOENT
  cacheinfo: Check cache properties are present in DT
  cacheinfo: Check sib_leaf in cache_leaves_are_shared()
  cacheinfo: Allow early level detection when DT/ACPI info is missing/broken
  cacheinfo: Add arm64 early level initializer implementation
  cacheinfo: Add arch specific early level initializer
---

a7b3a470fdea9f4a7daa5ae446c4e27c65f00aac
diff --cc drivers/base/cacheinfo.c
index f3903d0,45e3672..14aa62c
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@@ -472,20 -543,13 +543,19 @@@ int detect_cache_attributes(unsigned in
  	if (ret)
  		return ret;
  
- populate_leaves:
  	/*
 -	 * populate_cache_leaves() may completely setup the cache leaves and
 -	 * shared_cpu_map or it may leave it partially setup.
 +	 * If LLC is valid the cache leaves were already populated so just go to
 +	 * update the cpu map.
  	 */
 -	ret = populate_cache_leaves(cpu);
 -	if (ret)
 -		goto free_ci;
 +	if (!last_level_cache_is_valid(cpu)) {
 +		/*
 +		 * populate_cache_leaves() may completely setup the cache leaves and
 +		 * shared_cpu_map or it may leave it partially setup.
 +		 */
 +		ret = populate_cache_leaves(cpu);
 +		if (ret)
 +			goto free_ci;
 +	}
  
  	/*
  	 * For systems using DT for cache hierarchy, fw_token