From: Marc Zyngier Date: Wed, 4 May 2022 15:09:47 +0000 (+0100) Subject: Merge branch irq/gic-v3-5.19 into irq/irqchip-next X-Git-Tag: v6.1-rc5~1352^2^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a6ad8551b86137cbe266cbbeb512ee550ba3af6e;p=platform%2Fkernel%2Flinux-starfive.git Merge branch irq/gic-v3-5.19 into irq/irqchip-next * irq/gic-v3-5.19: : . : Misc improvements for GICv3: : : - Minimise the number of cases where we need to poll RWP : : - Allow the use of MMIO-based invalidation for LPIs : : - Track GICD/GICR mappings in /proc/iomem : : - Tighten the GICv3 DT binding to avoid endless discussions : on the list... : . irqchip/gic-v3: Claim iomem resources dt-bindings: interrupt-controller: arm,gic-v3: Make the v2 compat requirements explicit irqchip/gic-v3: Relax polling of GIC{R,D}_CTLR.RWP irqchip/gic-v3: Detect LPI invalidation MMIO registers irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES} Signed-off-by: Marc Zyngier --- a6ad8551b86137cbe266cbbeb512ee550ba3af6e