From: Chris Packham Date: Mon, 11 Feb 2019 01:19:56 +0000 (+1300) Subject: ARM: mvebu: x530: use MV_DDR_FREQ_SAR X-Git-Tag: v2019.04-rc2~17^2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a6ac775bae7fad1534ffe2b20244b7e7106b12b0;p=platform%2Fkernel%2Fu-boot.git ARM: mvebu: x530: use MV_DDR_FREQ_SAR MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware strapping. This also has the side effect of running the DDR clock in synchronous mode with the CPU core clock rather than from an independent PLL. We've seen this improve reliability in operation across a number of boards and temperature ranges. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index b34ae51..d7d1942 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -57,7 +57,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1866M, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */ MV_DDR_DIE_CAP_4GBIT, /* die capacity */ - MV_DDR_FREQ_933, /* frequency */ + MV_DDR_FREQ_SAR, /* frequency */ 0, 0, /* cas_l cas_wl */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_2T} }, /* timing */