From: Richard Henderson Date: Tue, 1 Mar 2016 16:59:32 +0000 (-0800) Subject: target-i386: Fix SMSW for 64-bit mode X-Git-Tag: TizenStudio_2.0_p2.4~27^2~6^2~8^2~121^2~4 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a657f79e32422634415c09f3f15c73d610297af5;p=sdk%2Femulator%2Fqemu.git target-i386: Fix SMSW for 64-bit mode In non-64-bit modes, the instruction always stores 16 bits. But in 64-bit mode, when the destination is a register, the instruction can write 32 or 64 bits. Tested-by: Hervé Poussineau Signed-off-by: Richard Henderson --- diff --git a/target-i386/translate.c b/target-i386/translate.c index 10cc2fa..b73c237 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7282,12 +7282,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, CASE_MODRM_OP(4): /* smsw */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); -#if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN - tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]) + 4); -#else - tcg_gen_ld32u_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0])); -#endif - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1); + tcg_gen_ld_tl(cpu_T0, cpu_env, offsetof(CPUX86State, cr[0])); + if (CODE64(s)) { + mod = (modrm >> 6) & 3; + ot = (mod != 3 ? MO_16 : s->dflag); + } else { + ot = MO_16; + } + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; CASE_MODRM_OP(6): /* lmsw */