From: aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Thu, 16 Apr 2009 11:51:11 +0000 (+0000)
Subject: target-mips: optimize gen_flt3_ldst()
X-Git-Tag: TizenStudio_2.0_p2.3~9159
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a649001e15f74bc1db7d404fb4468d0cb300d860;p=sdk%2Femulator%2Fqemu.git

target-mips: optimize gen_flt3_ldst()

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7126 c046a42c-6fe2-441c-8c8c-71466251a162
---

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 19c5181..003e9c6 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -7221,7 +7221,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
     const char *opn = "extended float load/store";
     int store = 0;
     TCGv t0 = tcg_temp_new();
-    TCGv t1 = tcg_temp_new();
 
     if (base == 0) {
         gen_load_gpr(t0, index);
@@ -7240,8 +7239,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
         {
             TCGv_i32 fp0 = tcg_temp_new_i32();
 
-            tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx);
-            tcg_gen_trunc_tl_i32(fp0, t1);
+            tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
+            tcg_gen_trunc_tl_i32(fp0, t0);
             gen_store_fpr32(fp0, fd);
             tcg_temp_free_i32(fp0);
         }
@@ -7275,11 +7274,13 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
         check_cop1x(ctx);
         {
             TCGv_i32 fp0 = tcg_temp_new_i32();
+            TCGv t1 = tcg_temp_new();
 
             gen_load_fpr32(fp0, fs);
             tcg_gen_extu_i32_tl(t1, fp0);
             tcg_gen_qemu_st32(t1, t0, ctx->mem_idx);
             tcg_temp_free_i32(fp0);
+            tcg_temp_free_i32(t1);
         }
         opn = "swxc1";
         store = 1;
@@ -7312,7 +7313,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
         break;
     }
     tcg_temp_free(t0);
-    tcg_temp_free(t1);
     MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd],
                regnames[index], regnames[base]);
 }