From: Davide Italiano Date: Wed, 12 Jul 2017 15:26:06 +0000 (+0000) Subject: [X86/FastIsel] Fall-back to SelectionDAG when lowering soft-floats. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a63981aaa9a99b34f436644bc023f77bd33b9a1d;p=platform%2Fupstream%2Fllvm.git [X86/FastIsel] Fall-back to SelectionDAG when lowering soft-floats. FastIsel can't handle them, so we would end up crashing during register class selection. Fixes PR26522. Differential Revision: https://reviews.llvm.org/D35272 llvm-svn: 307797 --- diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 621505a..ee9e781 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -3039,6 +3039,9 @@ bool X86FastISel::fastLowerArguments() { if (!Subtarget->is64Bit()) return false; + if (Subtarget->useSoftFloat()) + return false; + // Only handle simple cases. i.e. Up to 6 i32/i64 scalar arguments. unsigned GPRCnt = 0; unsigned FPRCnt = 0; diff --git a/llvm/test/CodeGen/X86/fastisel-softfloat.ll b/llvm/test/CodeGen/X86/fastisel-softfloat.ll new file mode 100644 index 0000000..e4330db --- /dev/null +++ b/llvm/test/CodeGen/X86/fastisel-softfloat.ll @@ -0,0 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc %s -o - | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define float @pr26522(float %pat) #0 { +; CHECK-LABEL: pr26522: +; CHECK: # BB#0: +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq + ret float %pat +} + +attributes #0 = { noinline optnone "target-features"="+soft-float" }