From: Homer Hsing <homer.xing@intel.com>
Date: Sun, 17 Feb 2013 05:23:41 +0000 (+0800)
Subject: Output the map from IR reg to ASM reg
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a637f16dec6a2eadb40a6ae6032ba5c4a41776a7;p=contrib%2Fbeignet.git

Output the map from IR reg to ASM reg

It is hard to guess the meaning of
  "mul(8) g10<1>d g0.6<0,1,0>d g3.2<0,1,0>d"
if you don't know the IR reg num of "g10" etc.

Now we can output the map from IR reg to ASM reg, such as
  "%0 g10.0D"
  "%1 g0.6D"
  "%2 g3.2D"
So you know the meaning is
  "mul %0 %1 %2"

By default, not output those message.
You can turn on by BVAR "OCL_OUTPUT_REG_ALLOC".

Signed-off-by: Homer Hsing <homer.xing@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
---

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 2710016..b4c9a65 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -342,6 +342,7 @@ namespace gbe
     p->pop();
   }
 
+  BVAR(OCL_OUTPUT_REG_ALLOC, false);
   BVAR(OCL_OUTPUT_ASM, false);
   bool GenContext::emitCode(void) {
     GenKernel *genKernel = static_cast<GenKernel*>(this->kernel);
@@ -350,6 +351,8 @@ namespace gbe
     if (UNLIKELY(ra->allocate(*this->sel) == false))
       return false;
     schedulePostRegAllocation(*this, *this->sel);
+    if (OCL_OUTPUT_REG_ALLOC)
+      ra->outputAllocation();
     this->emitStackPointer();
     this->emitInstructionStream();
     this->patchBranches();
diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp
index d6fdecb..10e4ab6 100644
--- a/backend/src/backend/gen_reg_allocation.cpp
+++ b/backend/src/backend/gen_reg_allocation.cpp
@@ -52,6 +52,8 @@ namespace gbe
     bool allocate(Selection &selection);
     /*! Return the Gen register from the selection register */
     GenRegister genReg(const GenRegister &reg);
+    /*! Output the register allocation */
+    void outputAllocation(void);
   private:
     /*! Expire one GRF interval. Return true if one was successfully expired */
     bool expireGRF(const GenRegInterval &limit);
@@ -668,6 +670,18 @@ namespace gbe
     return this->allocateGRFs(selection);
   }
 
+  INLINE void GenRegAllocator::Opaque::outputAllocation(void) {
+    std::cout << "## register allocation ##" << std::endl;
+    for(auto &i : RA) {
+        int vReg = (int)i.first;
+        int offst = (int)i.second / sizeof(float);
+        int reg = offst / 8;
+        int subreg = offst % 8;
+        std::cout << "%" << vReg << " g" << reg << "." << subreg << "D" << std::endl;
+    }
+    std::cout << std::endl;
+  }
+
   INLINE GenRegister setGenReg(const GenRegister &src, uint32_t grfOffset) {
     GenRegister dst;
     dst = src;
@@ -711,5 +725,9 @@ namespace gbe
     return this->opaque->genReg(reg);
   }
 
+  void GenRegAllocator::outputAllocation(void) {
+    this->opaque->outputAllocation();
+  }
+
 } /* namespace gbe */
 
diff --git a/backend/src/backend/gen_reg_allocation.hpp b/backend/src/backend/gen_reg_allocation.hpp
index b172995..b9859d7 100644
--- a/backend/src/backend/gen_reg_allocation.hpp
+++ b/backend/src/backend/gen_reg_allocation.hpp
@@ -47,6 +47,8 @@ namespace gbe
     bool allocate(Selection &selection);
     /*! Virtual to physical translation */
     GenRegister genReg(const GenRegister &reg);
+    /*! Output the register allocation */
+    void outputAllocation(void);
   private:
     /*! Actual implementation of the register allocator (use Pimpl) */
     class Opaque;