From: Brian Zhu <brian.zhu@amlogic.com>
Date: Fri, 7 Dec 2018 06:21:43 +0000 (+0800)
Subject: video: sr: add the missing bit mask for sr core1 [1/1]
X-Git-Tag: hardkernel-4.9.236-104~2067
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a601f6fc84db3b88e9c6e2a46c00394ff1802497;p=platform%2Fkernel%2Flinux-amlogic.git

video: sr: add the missing bit mask for sr core1 [1/1]

PD#SWPL-2948

Problem:
Miss the sr core1 bit mask to cause display abnormal

Solution:
Add the bit mask for sr core1

Verify:
Test pass by x301

Change-Id: I742d86b610a9748adad7c143d7a85c6796d3c8f7
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
---

diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c
index c526f61..463ff1c 100644
--- a/drivers/amlogic/media/video_sink/video.c
+++ b/drivers/amlogic/media/video_sink/video.c
@@ -6523,7 +6523,7 @@ SET_FILTER:
 			VPP_VD1_POSTBLEND |
 			VPP_PREBLEND_EN |
 			VPP_POSTBLEND_EN |
-			7);
+			0xf);
 		vpp_misc_save &=
 			((1 << 29) | VPP_CM_ENABLE |
 			(0x1ff << VPP_VD2_ALPHA_BIT) |
@@ -6533,7 +6533,7 @@ SET_FILTER:
 			VPP_VD1_POSTBLEND |
 			VPP_PREBLEND_EN |
 			VPP_POSTBLEND_EN |
-			7);
+			0xf);
 		if (vpp_misc_set != vpp_misc_save) {
 			/* vd1 need always enable pre bld */
 			if (vpp_misc_set & VPP_VD1_POSTBLEND)