From: Andy Shevchenko Date: Tue, 13 Jul 2021 15:25:22 +0000 (+0200) Subject: media: atomisp: Move MIPI_PORT_LANES to the only user X-Git-Tag: accepted/tizen/unified/20230118.172025~6519^2~51^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a5e5ceae597ba1df8a2a5720f80bf690c96805b0;p=platform%2Fkernel%2Flinux-rpi.git media: atomisp: Move MIPI_PORT_LANES to the only user Move MIPI_PORT_LANES to the only user of it, i.e. pci/runtime/isys/src/rx.c. Link: https://lore.kernel.org/linux-media/20210713152523.19902-4-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko Signed-off-by: Mauro Carvalho Chehab --- diff --git a/drivers/staging/media/atomisp/pci/isp2400_input_system_local.h b/drivers/staging/media/atomisp/pci/isp2400_input_system_local.h index 21f11bd..2614b89 100644 --- a/drivers/staging/media/atomisp/pci/isp2400_input_system_local.h +++ b/drivers/staging/media/atomisp/pci/isp2400_input_system_local.h @@ -362,17 +362,6 @@ static const hrt_address __maybe_unused MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = { 0x00000200UL }; -static const mipi_lane_cfg_t MIPI_PORT_LANES[N_RX_MODE][N_MIPI_PORT_ID] = { - {MIPI_4LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, - {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, - {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, - {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, - {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_2LANE_CFG}, - {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, - {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, - {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG} -}; - static const hrt_address __maybe_unused SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = { 0x00001000UL, 0x00002000UL, diff --git a/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c b/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c index 60b98c1..af153c3 100644 --- a/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c +++ b/drivers/staging/media/atomisp/pci/runtime/isys/src/rx.c @@ -476,6 +476,17 @@ unsigned int ia_css_csi2_calculate_input_system_alignment( #endif #if !defined(ISP2401) +static const mipi_lane_cfg_t MIPI_PORT_LANES[N_RX_MODE][N_MIPI_PORT_ID] = { + {MIPI_4LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_2LANE_CFG}, + {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, + {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, + {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG} +}; + void ia_css_isys_rx_configure(const rx_cfg_t *config, const enum ia_css_input_mode input_mode) {