From: Jose Maria Casanova Crespo Date: Wed, 24 Jul 2019 20:01:00 +0000 (+0200) Subject: v3d: writes to magic registers aren't RF writes after THREND X-Git-Tag: upstream/19.3.0~2207 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a5df0fa0b1d821a3d3f6f483b0c712aff3dad364;p=platform%2Fupstream%2Fmesa.git v3d: writes to magic registers aren't RF writes after THREND Shaders must not attempt to write to the register files in the last three instructions, but that doesn't include the magic registers: nop ; nop ; thrsw; ldtmu.- *** ERROR *** nop ; nop nop ; nop v2: Simplify validation rules. (Eric Anholt) v3: Adjust validation even more. (Eric Anholt) Reviewed-by: Eric Anholt --- diff --git a/src/broadcom/compiler/qpu_validate.c b/src/broadcom/compiler/qpu_validate.c index fb2ed12..24be4fd 100644 --- a/src/broadcom/compiler/qpu_validate.c +++ b/src/broadcom/compiler/qpu_validate.c @@ -258,8 +258,10 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state, struct qinst *qinst) fail_instr(state, "RF write after THREND"); } - if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) + if (v3d_qpu_sig_writes_address(devinfo, &inst->sig) && + !inst->sig_magic) { fail_instr(state, "RF write after THREND"); + } /* GFXH-1625: No TMUWT in the last instruction */ if (state->last_thrsw_ip - state->ip == 2 &&