From: Michel Dänzer Date: Wed, 18 Sep 2013 13:39:41 +0000 (+0200) Subject: drm/radeon/cik: Fix encoding of number of banks in tiling configuration info X-Git-Tag: accepted/tizen/common/20141203.182822~1379^2~1^2~14 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a537314e0b539e22934d3cffeb0b1f476e56491c;p=platform%2Fkernel%2Flinux-arm64.git drm/radeon/cik: Fix encoding of number of banks in tiling configuration info There are multiple valid values, not just 0 or 1. Required to properly support 2D tiling in the userspace drivers. Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index c0714d7..5e6802d 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -2845,10 +2845,8 @@ static void cik_gpu_init(struct radeon_device *rdev) rdev->config.cik.tile_config |= (3 << 0); break; } - if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) - rdev->config.cik.tile_config |= 1 << 4; - else - rdev->config.cik.tile_config |= 0 << 4; + rdev->config.cik.tile_config |= + ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; rdev->config.cik.tile_config |= ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; rdev->config.cik.tile_config |=