From: Maciej W. Rozycki Date: Tue, 2 May 2017 10:53:30 +0000 (+0100) Subject: MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassembly X-Git-Tag: binutils-2_29~617 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a4ddc54ec1cd187c844ca631fe0315bf1d78e96f;p=external%2Fbinutils.git MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassembly Correct the disassembly of the PC-relative immediate argument of the MIPS16 synthetic LA, LW, DLA and LD instructions and do not mask the LSB, which in this case is a part of the data address rather than the ISA bit and has to be fully presented. opcodes/ * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps and branches and not synthetic data instructions. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the disassembly of PC-relative LA and LW synthetic instructions. --- diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 5fdcd4d..aef436d 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2017-05-02 Maciej W. Rozycki + + * testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the + disassembly of PC-relative LA and LW synthetic instructions. + 2017-05-02 Nick Clifton PR 21440 diff --git a/binutils/testsuite/binutils-all/mips/mips16-undecoded.d b/binutils/testsuite/binutils-all/mips/mips16-undecoded.d index 42a5cdf..b455419 100644 --- a/binutils/testsuite/binutils-all/mips/mips16-undecoded.d +++ b/binutils/testsuite/binutils-all/mips/mips16-undecoded.d @@ -11,11 +11,11 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> f008 0231 addiu v0,sp,16401 [0-9a-f]+ <[^>]*> f008 0251 addiu v0,sp,16401 [0-9a-f]+ <[^>]*> f008 0291 addiu v0,sp,16401 -[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004024 -[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004028 -[0-9a-f]+ <[^>]*> f008 0a31 la v0,0000402c -[0-9a-f]+ <[^>]*> f008 0a51 la v0,00004030 -[0-9a-f]+ <[^>]*> f008 0a91 la v0,00004034 +[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004025 +[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004029 +[0-9a-f]+ <[^>]*> f008 0a31 la v0,0000402d +[0-9a-f]+ <[^>]*> f008 0a51 la v0,00004031 +[0-9a-f]+ <[^>]*> f008 0a91 la v0,00004035 [0-9a-f]+ <[^>]*> f008 1011 b 0000804e [0-9a-f]+ <[^>]*> f008 1011 b 00008052 [0-9a-f]+ <[^>]*> f008 1031 b 00008056 @@ -64,11 +64,11 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> f008 9231 lw v0,16401\(sp\) [0-9a-f]+ <[^>]*> f008 9251 lw v0,16401\(sp\) [0-9a-f]+ <[^>]*> f008 9291 lw v0,16401\(sp\) -[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040f8 -[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040fc -[0-9a-f]+ <[^>]*> f008 b231 lw v0,00004100 -[0-9a-f]+ <[^>]*> f008 b251 lw v0,00004104 -[0-9a-f]+ <[^>]*> f008 b291 lw v0,00004108 +[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040f9 +[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040fd +[0-9a-f]+ <[^>]*> f008 b231 lw v0,00004101 +[0-9a-f]+ <[^>]*> f008 b251 lw v0,00004105 +[0-9a-f]+ <[^>]*> f008 b291 lw v0,00004109 [0-9a-f]+ <[^>]*> f008 d211 sw v0,16401\(sp\) [0-9a-f]+ <[^>]*> f008 d211 sw v0,16401\(sp\) [0-9a-f]+ <[^>]*> f008 d231 sw v0,16401\(sp\) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ad3a01a..dcde282 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-05-02 Maciej W. Rozycki + + * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps + and branches and not synthetic data instructions. + 2017-05-02 Bernd Edlinger * arm-dis.c (print_insn_thumb32): Fix value_in_comment. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 4a08d8a..289f501 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -1281,9 +1281,10 @@ print_insn_arg (struct disassemble_info *info, pcrel_op = (const struct mips_pcrel_operand *) operand; info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval); - /* Preserve the ISA bit for the GDB disassembler, - otherwise clear it. */ - if (info->flavour != bfd_target_unknown_flavour) + /* For jumps and branches clear the ISA bit except for + the GDB disassembler. */ + if (pcrel_op->include_isa_bit + && info->flavour != bfd_target_unknown_flavour) info->target &= -2; (*info->print_address_func) (info->target, info);