From: Yanteng Si Date: Wed, 7 Jun 2023 09:21:52 +0000 (+0800) Subject: ALSA: hda/intel: Workaround for WALLCLK register for loongson controller X-Git-Tag: v6.6.7~2394^2~16^2~24 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a4d2b8537845c9a4f4b16dd31793af9c08548341;p=platform%2Fkernel%2Flinux-starfive.git ALSA: hda/intel: Workaround for WALLCLK register for loongson controller On loongson controller, the value of WALLCLK register is always 0, which is meaningless, so we return directly. Signed-off-by: Yanteng Si Signed-off-by: Yingkun Meng Acked-by: Huacai Chen Link: https://lore.kernel.org/r/185df71ef413ab190460eb377703214ee7288aeb.1686128807.git.siyanteng@loongson.cn Signed-off-by: Takashi Iwai --- diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index fc4787c..ef83177 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -655,6 +655,13 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) unsigned int pos; snd_pcm_uframes_t hwptr, target; + /* + * The value of the WALLCLK register is always 0 + * on the Loongson controller, so we return directly. + */ + if (chip->driver_type == AZX_DRIVER_LOONGSON) + return 1; + wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) return -1; /* bogus (too early) interrupt */