From: Andrzej Hajda Date: Fri, 25 Nov 2016 14:07:16 +0000 (+0100) Subject: drm/bridge/sii8620: fix CBUS bring-up sequence X-Git-Tag: submit/tizen/20161216.052309~38 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a4cf9e542594ce69139f21d96adb2469776c4929;p=platform%2Fkernel%2Flinux-exynos.git drm/bridge/sii8620: fix CBUS bring-up sequence In case of MHL3 CBUS is bring-up already in sii8620_got_ecbus_speed. Change-Id: I4abafa944113528eb6cc71799a35f4215aeac428 Signed-off-by: Andrzej Hajda --- diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c index c9341a4fe67c..d620e853670a 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.c +++ b/drivers/gpu/drm/bridge/sil-sii8620.c @@ -451,10 +451,6 @@ static void sii8620_mr_xdevcap(struct sii8620 *ctx) { sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap, MHL_XDC_SIZE); - - sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE), - MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT); - sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP); } static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx,