From: Joonyoung Shim Date: Wed, 1 Oct 2014 12:27:35 +0000 (+0900) Subject: odroid: fix g2d sclk rate X-Git-Tag: submit/tizen_common/20150115.132736~26 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a47a37bf90d0bef6a14663525ea9b4233ca12388;p=platform%2Fkernel%2Fu-boot.git odroid: fix g2d sclk rate G2D core should be provided 200MHz clock rate. Change-Id: If06eb7d4433d302767f04e7c8b487cdcd32321a4 Signed-off-by: Joonyoung Shim --- diff --git a/board/samsung/common/exynos4-dt.c b/board/samsung/common/exynos4-dt.c index 27be6a70a0..fd92076b1b 100644 --- a/board/samsung/common/exynos4-dt.c +++ b/board/samsung/common/exynos4-dt.c @@ -408,12 +408,12 @@ static void board_clock_init(void) * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ - set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); clrsetbits_le32(&clk->div_dmc1, clr, set); diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index b7d23817e1..1554b9d230 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -248,12 +248,12 @@ static void board_clock_init(void) * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ - set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); clrsetbits_le32(&clk->div_dmc1, clr, set);