From: Yinbo Zhu Date: Mon, 11 Mar 2019 02:16:36 +0000 (+0000) Subject: mmc: sdhci-of-esdhc: add erratum eSDHC5 support X-Git-Tag: v5.15~6453^2~78 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a46e42712596b51874f04c73f1cdf1017f88df52;p=platform%2Fkernel%2Flinux-starfive.git mmc: sdhci-of-esdhc: add erratum eSDHC5 support Software writing to the Transfer Type configuration register (system clock domain) can cause a setup/hold violation in the CRC flops (card clock domain), which can cause write accesses to be sent with corrupt CRC values. This issue occurs only for write preceded by read. this erratum is to fix this issue. Signed-off-by: Yinbo Zhu Acked-by: Adrian Hunter Signed-off-by: Ulf Hansson --- diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index e8cb7a9..b3310ea 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -1075,6 +1075,9 @@ static int sdhci_esdhc_probe(struct platform_device *pdev) if (esdhc->vendor_ver > VENDOR_V_22) host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; + if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) + host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST; + if (of_device_is_compatible(np, "fsl,p5040-esdhc") || of_device_is_compatible(np, "fsl,p5020-esdhc") || of_device_is_compatible(np, "fsl,p4080-esdhc") ||