From: Wanpeng Li Date: Fri, 31 Jul 2020 03:12:20 +0000 (+0800) Subject: KVM: LAPIC: Set the TDCR settable bits X-Git-Tag: v5.10.7~1931^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a445fc457d2886a1264ec09c34f4000d1b30784d;p=platform%2Fkernel%2Flinux-rpi.git KVM: LAPIC: Set the TDCR settable bits It is a little different between Intel and AMD, Intel's bit 2 is 0 and AMD is reserved. On bare-metal, Intel will refuse to set APIC_TDCR once bits except 0, 1, 3 are setting, however, AMD will accept bits 0, 1, 3 and ignore other bits setting as patch does. Before the patch, we can get back anything what we set to the APIC_TDCR, this patch improves it. Signed-off-by: Wanpeng Li Message-Id: <1596165141-28874-2-git-send-email-wanpengli@tencent.com> Signed-off-by: Paolo Bonzini --- diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index d5fb2ea..bd16e31 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2066,7 +2066,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) case APIC_TDCR: { uint32_t old_divisor = apic->divide_count; - kvm_lapic_set_reg(apic, APIC_TDCR, val); + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); update_divide_count(apic); if (apic->divide_count != old_divisor && apic->lapic_timer.period) {