From: Hongyu Wang <hongyu.wang@intel.com>
Date: Fri, 15 Apr 2022 02:51:06 +0000 (+0800)
Subject: i386: Correct target attribute for crc32 intrinsics
X-Git-Tag: upstream/12.2.0~523
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a335a94a1bf49dcb3c966af05cd68be6ee36277e;p=platform%2Fupstream%2Fgcc.git

i386: Correct target attribute for crc32 intrinsics

Complile _mm_crc32_u8/16/32/64 intrinsics with -mcrc32
would meet target specific option mismatch. Correct target pragma
to fix.

gcc/ChangeLog:

	* config/i386/smmintrin.h: Correct target pragma from sse4.1
	and sse4.2 to crc32 for crc32 intrinsics.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/crc32-6.c: Adjust dg-error message.
	* gcc.target/i386/crc32-7.c: New test.
---

diff --git a/gcc/config/i386/smmintrin.h b/gcc/config/i386/smmintrin.h
index b42b212..eb6a451 100644
--- a/gcc/config/i386/smmintrin.h
+++ b/gcc/config/i386/smmintrin.h
@@ -810,17 +810,11 @@ _mm_cmpgt_epi64 (__m128i __X, __m128i __Y)
 
 #include <popcntintrin.h>
 
-#ifndef __SSE4_1__
+#ifndef __CRC32__
 #pragma GCC push_options
-#pragma GCC target("sse4.1")
-#define __DISABLE_SSE4_1__
-#endif /* __SSE4_1__ */
-
-#ifndef __SSE4_2__
-#pragma GCC push_options
-#pragma GCC target("sse4.2")
-#define __DISABLE_SSE4_2__
-#endif /* __SSE4_1__ */
+#pragma GCC target("crc32")
+#define __DISABLE_CRC32__
+#endif /* __CRC32__ */
 
 /* Accumulate CRC32 (polynomial 0x11EDC6F41) value.  */
 extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
@@ -849,14 +843,9 @@ _mm_crc32_u64 (unsigned long long __C, unsigned long long __V)
 }
 #endif
 
-#ifdef __DISABLE_SSE4_2__
-#undef __DISABLE_SSE4_2__
+#ifdef __DISABLE_CRC32__
+#undef __DISABLE_CRC32__
 #pragma GCC pop_options
-#endif /* __DISABLE_SSE4_2__ */
-
-#ifdef __DISABLE_SSE4_1__
-#undef __DISABLE_SSE4_1__
-#pragma GCC pop_options
-#endif /* __DISABLE_SSE4_1__ */
+#endif /* __DISABLE_CRC32__ */
 
 #endif /* _SMMINTRIN_H_INCLUDED */
diff --git a/gcc/testsuite/gcc.target/i386/crc32-6.c b/gcc/testsuite/gcc.target/i386/crc32-6.c
index 464e344..7f2b42d 100644
--- a/gcc/testsuite/gcc.target/i386/crc32-6.c
+++ b/gcc/testsuite/gcc.target/i386/crc32-6.c
@@ -10,4 +10,4 @@ test_mm_crc32_u8 (unsigned int CRC, unsigned char V)
   return _mm_crc32_u8 (CRC, V);
 }
 
-/* { dg-error "needs isa option -mcrc32" "" { target *-*-* } 0  } */
+/* { dg-error "target specific option mismatch" "" { target *-*-* } 0  } */
diff --git a/gcc/testsuite/gcc.target/i386/crc32-7.c b/gcc/testsuite/gcc.target/i386/crc32-7.c
new file mode 100644
index 0000000..2e310e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/crc32-7.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcrc32" } */
+/* { dg-final { scan-assembler "crc32b\[^\\n\]*eax" } } */
+/* { dg-final { scan-assembler "crc32w\[^\\n\]*eax" } } */
+/* { dg-final { scan-assembler "crc32l\[^\\n\]*eax" } } */
+/* { dg-final { scan-assembler "crc32q\[^\\n\]*rax" { target { ! ia32 } } } } */
+
+#include <immintrin.h>
+
+unsigned int
+test_mm_crc32_u8 (unsigned int CRC, unsigned char V)
+{
+  return _mm_crc32_u8 (CRC, V);
+}
+
+unsigned int
+test_mm_crc32_u16 (unsigned int CRC, unsigned short V)
+{
+  return _mm_crc32_u16 (CRC, V);
+}
+
+unsigned int
+test_mm_crc32_u32 (unsigned int CRC, unsigned int V)
+{
+  return _mm_crc32_u32 (CRC, V);
+}
+
+#ifdef __x86_64__
+unsigned long long
+test_mm_crc32_u64 (unsigned long long CRC, unsigned long long V)
+{
+  return _mm_crc32_u64 (CRC, V);
+}
+#endif