From: Matthias Braun Date: Wed, 24 Aug 2016 22:34:06 +0000 (+0000) Subject: MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it X-Git-Tag: llvmorg-4.0.0-rc1~11532 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a319e2cae0298cf710d65dc5c82cc1549b36658e;p=platform%2Fupstream%2Fllvm.git MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it llvm-svn: 279680 --- diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index f61b3c9..31bb1dc 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -281,14 +281,6 @@ void MIRParserImpl::createDummyFunction(StringRef Name, Module &M) { new UnreachableInst(Context, BB); } -static bool hasPHI(const MachineFunction &MF) { - for (const MachineBasicBlock &MBB : MF) - for (const MachineInstr &MI : MBB) - if (MI.isPHI()) - return true; - return false; -} - static bool isSSA(const MachineFunction &MF) { const MachineRegisterInfo &MRI = MF.getRegInfo(); for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { @@ -301,8 +293,20 @@ static bool isSSA(const MachineFunction &MF) { void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) { MachineFunctionProperties &Properties = MF.getProperties(); - if (!hasPHI(MF)) + + bool HasPHI = false; + bool HasInlineAsm = false; + for (const MachineBasicBlock &MBB : MF) { + for (const MachineInstr &MI : MBB) { + if (MI.isPHI()) + HasPHI = true; + if (MI.isInlineAsm()) + HasInlineAsm = true; + } + } + if (!HasPHI) Properties.set(MachineFunctionProperties::Property::NoPHIs); + MF.setHasInlineAsm(HasInlineAsm); if (isSSA(MF)) Properties.set(MachineFunctionProperties::Property::IsSSA); @@ -320,7 +324,6 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) { if (YamlMF.Alignment) MF.setAlignment(YamlMF.Alignment); MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice); - MF.setHasInlineAsm(YamlMF.HasInlineAsm); if (YamlMF.AllVRegsAllocated) MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated); diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index 795f1ca..1cd4eb9 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -174,7 +174,6 @@ void MIRPrinter::print(const MachineFunction &MF) { YamlMF.Name = MF.getName(); YamlMF.Alignment = MF.getAlignment(); YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); - YamlMF.HasInlineAsm = MF.hasInlineAsm(); YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty( MachineFunctionProperties::Property::AllVRegsAllocated); diff --git a/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir b/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir index bb9bdb0..65d8acb 100644 --- a/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir +++ b/llvm/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir @@ -28,7 +28,6 @@ name: promote-load-from-store alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: false liveins: @@ -84,7 +83,6 @@ body: | name: store-pair alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: false liveins: diff --git a/llvm/test/CodeGen/AArch64/movimm-wzr.mir b/llvm/test/CodeGen/AArch64/movimm-wzr.mir index 1264f26..c26643e 100644 --- a/llvm/test/CodeGen/AArch64/movimm-wzr.mir +++ b/llvm/test/CodeGen/AArch64/movimm-wzr.mir @@ -15,7 +15,6 @@ name: test_mov_0 alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: false frameInfo: diff --git a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir index 2682daa..144961b 100644 --- a/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ b/llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -79,7 +79,6 @@ name: f alignment: 1 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true liveins: diff --git a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir index 588ec5d..0ad0e9d 100644 --- a/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir +++ b/llvm/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir @@ -33,7 +33,6 @@ name: test_tlsdesc_callseq_length alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: false liveins: diff --git a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir index ca330cb..7a0d298 100644 --- a/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ b/llvm/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -90,7 +90,6 @@ name: f alignment: 1 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true liveins: diff --git a/llvm/test/CodeGen/MIR/Generic/machine-function.mir b/llvm/test/CodeGen/MIR/Generic/machine-function.mir index 64802a1..f9001cc 100644 --- a/llvm/test/CodeGen/MIR/Generic/machine-function.mir +++ b/llvm/test/CodeGen/MIR/Generic/machine-function.mir @@ -24,7 +24,6 @@ # CHECK: name: foo # CHECK-NEXT: alignment: # CHECK-NEXT: exposesReturnsTwice: false -# CHECK-NEXT: hasInlineAsm: false # CHECK: ... name: foo body: | @@ -34,7 +33,6 @@ body: | # CHECK: name: bar # CHECK-NEXT: alignment: # CHECK-NEXT: exposesReturnsTwice: false -# CHECK-NEXT: hasInlineAsm: false # CHECK: ... name: bar body: | @@ -44,7 +42,6 @@ body: | # CHECK: name: func # CHECK-NEXT: alignment: 8 # CHECK-NEXT: exposesReturnsTwice: false -# CHECK-NEXT: hasInlineAsm: false # CHECK: ... name: func alignment: 8 @@ -55,12 +52,10 @@ body: | # CHECK: name: func2 # CHECK-NEXT: alignment: 16 # CHECK-NEXT: exposesReturnsTwice: true -# CHECK-NEXT: hasInlineAsm: true # CHECK: ... name: func2 alignment: 16 exposesReturnsTwice: true -hasInlineAsm: true body: | bb.0: ... diff --git a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir index ddf4212..e9f2966 100644 --- a/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir +++ b/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir @@ -175,7 +175,6 @@ name: test0a alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: @@ -221,7 +220,6 @@ body: | name: test0b alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: @@ -265,7 +263,6 @@ body: | name: test1a alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: @@ -313,7 +310,6 @@ body: | name: test1b alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: @@ -361,7 +357,6 @@ body: | name: test2a alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: @@ -409,7 +404,6 @@ body: | name: test2b alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: @@ -457,7 +451,6 @@ body: | name: test3 alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: @@ -505,7 +498,6 @@ body: | name: test4 alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: @@ -617,7 +609,6 @@ body: | name: testBB alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: diff --git a/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir b/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir index bd9365b..fe0740e 100644 --- a/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir +++ b/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir @@ -10,7 +10,6 @@ ... --- name: test -hasInlineAsm: true tracksRegLiveness: true liveins: - { reg: '%rdi' } diff --git a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir index 95b1057..2bc8250 100644 --- a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir @@ -19,7 +19,6 @@ ... --- name: test -hasInlineAsm: true tracksRegLiveness: true liveins: - { reg: '%edi' } diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir index c3f4fca..a5c7b48 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir @@ -10,7 +10,6 @@ ... --- name: test -hasInlineAsm: true tracksRegLiveness: true liveins: - { reg: '%rdi' } diff --git a/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir b/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir index 9e307f8..fce8c1a 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir @@ -10,7 +10,6 @@ ... --- name: test -hasInlineAsm: true tracksRegLiveness: true liveins: - { reg: '%rdi' } diff --git a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir index f0e8d1f..d84cebfc 100644 --- a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir +++ b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir @@ -19,7 +19,6 @@ ... --- name: test -hasInlineAsm: true tracksRegLiveness: true liveins: - { reg: '%rdi' } @@ -36,7 +35,6 @@ body: | ... --- name: test2 -hasInlineAsm: true tracksRegLiveness: true liveins: - { reg: '%rdi' } diff --git a/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir b/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir index 2ba3288..7a0994d 100644 --- a/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir +++ b/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir @@ -10,7 +10,6 @@ ... --- name: test -hasInlineAsm: true tracksRegLiveness: true liveins: - { reg: '%rdi' } diff --git a/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir b/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir index 05502ff..84a38bf 100644 --- a/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir +++ b/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir @@ -10,7 +10,6 @@ ... --- name: test -hasInlineAsm: true tracksRegLiveness: true liveins: - { reg: '%rdi' } diff --git a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir index 9e750eb..a49251b 100644 --- a/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir +++ b/llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -44,7 +44,6 @@ name: mm_update_next_owner alignment: 4 exposesReturnsTwice: false -hasInlineAsm: true allVRegsAllocated: true tracksRegLiveness: true liveins: diff --git a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir index 0bf7b95..45ff51d 100644 --- a/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ b/llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -26,7 +26,6 @@ name: test1 alignment: 4 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true frameInfo: diff --git a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir index dce1e04..bab2ff2 100644 --- a/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir +++ b/llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir @@ -39,7 +39,6 @@ name: main alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false tracksRegLiveness: true registers: - { id: 0, class: g8rc_and_g8rc_nox0 } diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir index 619954e..d4b83b9 100644 --- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -32,7 +32,6 @@ name: fn1 alignment: 2 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: false tracksRegLiveness: true registers: diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir index aaf1284..ea898ec 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir @@ -157,7 +157,6 @@ name: add alignment: 4 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true liveins: diff --git a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir index 750187e..920d653 100644 --- a/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir +++ b/llvm/test/DebugInfo/MIR/X86/live-debug-values.mir @@ -159,7 +159,6 @@ name: main alignment: 4 exposesReturnsTwice: false -hasInlineAsm: false allVRegsAllocated: true tracksRegLiveness: true liveins: