From: Maciej W. Rozycki <macro@embecosm.com>
Date: Wed, 3 Nov 2021 17:04:19 +0000 (+0000)
Subject: RISC-V: Fix register class subset checks for CLASS_MAX_NREGS
X-Git-Tag: upstream/12.2.0~3823
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a31056e9196daf0a5b0e92d171b5227cc994103b;p=platform%2Fupstream%2Fgcc.git

RISC-V: Fix register class subset checks for CLASS_MAX_NREGS

Fix the register class subset checks in the determination of the maximum
number of consecutive registers needed to hold a value of a given mode.

The number depends on whether a register is a general-purpose or a
floating-point register, so check whether the register class requested
is a subset (argument 1 to `reg_class_subset_p') rather than superset
(argument 2) of GR_REGS or FP_REGS class respectively.

	gcc/
	* config/riscv/riscv.c (riscv_class_max_nregs): Swap the
	arguments to `reg_class_subset_p'.
---

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 5387bfc..a545dbf 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4810,10 +4810,10 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
 static unsigned char
 riscv_class_max_nregs (reg_class_t rclass, machine_mode mode)
 {
-  if (reg_class_subset_p (FP_REGS, rclass))
+  if (reg_class_subset_p (rclass, FP_REGS))
     return riscv_hard_regno_nregs (FP_REG_FIRST, mode);
 
-  if (reg_class_subset_p (GR_REGS, rclass))
+  if (reg_class_subset_p (rclass, GR_REGS))
     return riscv_hard_regno_nregs (GP_REG_FIRST, mode);
 
   return 0;