From: Andre Vieira Date: Wed, 15 May 2019 15:54:23 +0000 (+0100) Subject: [PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav X-Git-Tag: binutils-2_33~1239 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a302e574182dc12e95850dec078dac93701f1bde;p=external%2Fbinutils.git [PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav gas/ChangeLog: 2019-05-16 Andre Vieira * config/tc-arm.c (struct asm_opcode): Make avalue a full int. (BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors. (enum operand_parse_code): Handle new operands. (parse_operands): Likewise. (M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx, M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx, M_MNEM_vmlsdavax): Define new encodings. (NEON_SHAPE_DEF): Add new shape. (neon_check_type): Use BAD_SIMD_TYPE. (mve_encode_rqq): New encoding helper function. (do_mve_vabav, do_mve_vmladav): New encoding functions. (mCEF): New MACRO. * testsuite/gas/arm/mve-vabav-bad.d: New test. * testsuite/gas/arm/mve-vabav-bad.l: New test. * testsuite/gas/arm/mve-vabav-bad.s: New test. * testsuite/gas/arm/mve-vmladav-bad.d: New test. * testsuite/gas/arm/mve-vmladav-bad.l: New test. * testsuite/gas/arm/mve-vmladav-bad.s: New test. * testsuite/gas/arm/mve-vmlav-bad.d: New test. * testsuite/gas/arm/mve-vmlav-bad.l: New test. * testsuite/gas/arm/mve-vmlav-bad.s: New test. * testsuite/gas/arm/mve-vmlsdav-bad.d: New test. * testsuite/gas/arm/mve-vmlsdav-bad.l: New test. * testsuite/gas/arm/mve-vmlsdav-bad.s: New test. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index c94dd33..dafb420 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,32 @@ 2019-05-16 Andre Vieira + * config/tc-arm.c (struct asm_opcode): Make avalue a full int. + (BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors. + (enum operand_parse_code): Handle new operands. + (parse_operands): Likewise. + (M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx, + M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx, + M_MNEM_vmlsdavax): Define new encodings. + (NEON_SHAPE_DEF): Add new shape. + (neon_check_type): Use BAD_SIMD_TYPE. + (mve_encode_rqq): New encoding helper function. + (do_mve_vabav, do_mve_vmladav): New encoding functions. + (mCEF): New MACRO. + * testsuite/gas/arm/mve-vabav-bad.d: New test. + * testsuite/gas/arm/mve-vabav-bad.l: New test. + * testsuite/gas/arm/mve-vabav-bad.s: New test. + * testsuite/gas/arm/mve-vmladav-bad.d: New test. + * testsuite/gas/arm/mve-vmladav-bad.l: New test. + * testsuite/gas/arm/mve-vmladav-bad.s: New test. + * testsuite/gas/arm/mve-vmlav-bad.d: New test. + * testsuite/gas/arm/mve-vmlav-bad.l: New test. + * testsuite/gas/arm/mve-vmlav-bad.s: New test. + * testsuite/gas/arm/mve-vmlsdav-bad.d: New test. + * testsuite/gas/arm/mve-vmlsdav-bad.l: New test. + * testsuite/gas/arm/mve-vmlsdav-bad.s: New test. + +2019-05-16 Andre Vieira + * config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant. (insns): Change vabs and vneg entries to accept MVE variants. * testsuite/gas/arm/mve-vabsneg-bad-1.d: New test. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 8b1e9fc..39e81ba 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -708,7 +708,7 @@ struct asm_opcode unsigned int tag : 4; /* Basic instruction code. */ - unsigned int avalue : 28; + unsigned int avalue; /* Thumb-format instruction code. */ unsigned int tvalue; @@ -851,6 +851,8 @@ struct asm_opcode #define BAD_ARGS _("bad arguments to instruction") #define BAD_SP _("r13 not allowed here") #define BAD_PC _("r15 not allowed here") +#define BAD_ODD _("Odd register not allowed here") +#define BAD_EVEN _("Even register not allowed here") #define BAD_COND _("instruction cannot be conditional") #define BAD_OVERLAP _("registers may not be the same") #define BAD_HIREG _("lo register required") @@ -884,6 +886,7 @@ struct asm_opcode " operand") #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \ " operand") +#define BAD_SIMD_TYPE _("bad type in SIMD instruction") static struct hash_control * arm_ops_hsh; static struct hash_control * arm_cond_hsh; @@ -6714,8 +6717,12 @@ enum operand_parse_code */ OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or GPR (no SP/SP) */ + OP_RMQ, /* MVE vector register. */ + /* New operands for Armv8.1-M Mainline. */ OP_LR, /* ARM LR register */ + OP_RRe, /* ARM register, only even numbered. */ + OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */ OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */ OP_REGLST, /* ARM register list */ @@ -6973,6 +6980,8 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) case OP_RRnpc: case OP_RRnpcsp: case OP_oRR: + case OP_RRe: + case OP_RRo: case OP_LR: case OP_oLR: case OP_RR: po_reg_or_fail (REG_TYPE_RN); break; @@ -7037,6 +7046,9 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) po_reg_or_fail (REG_TYPE_NSDQ); inst.error = 0; break; + case OP_RMQ: + po_reg_or_fail (REG_TYPE_MQ); + break; /* Neon scalar. Using an element size of 8 means that some invalid scalars are accepted here, so deal with those in later code. */ case OP_RNSC: po_scalar_or_goto (8, failure); break; @@ -7557,6 +7569,24 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) inst.error = _("operand must be LR register"); break; + case OP_RRe: + if (inst.operands[i].isreg + && (inst.operands[i].reg & 0x00000001) != 0) + inst.error = BAD_ODD; + break; + + case OP_RRo: + if (inst.operands[i].isreg) + { + if ((inst.operands[i].reg & 0x00000001) != 1) + inst.error = BAD_EVEN; + else if (inst.operands[i].reg == REG_SP) + as_tsktsk (MVE_BAD_SP); + else if (inst.operands[i].reg == REG_PC) + inst.error = BAD_PC; + } + break; + default: break; } @@ -13793,6 +13823,17 @@ do_t_loloop (void) } } +/* MVE instruction encoder helpers. */ +#define M_MNEM_vabav 0xee800f01 +#define M_MNEM_vmladav 0xeef00e00 +#define M_MNEM_vmladava 0xeef00e20 +#define M_MNEM_vmladavx 0xeef01e00 +#define M_MNEM_vmladavax 0xeef01e20 +#define M_MNEM_vmlsdav 0xeef00e01 +#define M_MNEM_vmlsdava 0xeef00e21 +#define M_MNEM_vmlsdavx 0xeef01e01 +#define M_MNEM_vmlsdavax 0xeef01e21 + /* Neon instruction encoder helpers. */ /* Encodings for the different types for various Neon opcodes. */ @@ -13956,6 +13997,7 @@ NEON_ENC_TAB - a table used to drive neon_select_shape. */ #define NEON_SHAPE_DEF \ + X(3, (R, Q, Q), QUAD), \ X(3, (D, D, D), DOUBLE), \ X(3, (Q, Q, Q), QUAD), \ X(3, (D, D, I), DOUBLE), \ @@ -14683,7 +14725,7 @@ neon_check_type (unsigned els, enum neon_shape ns, ...) if ((given_type & types_allowed) == 0) { - first_error (_("bad type in SIMD instruction")); + first_error (BAD_SIMD_TYPE); return badtype; } } @@ -15165,6 +15207,19 @@ mve_encode_qqr (int size, int fp) inst.is_neon = 1; } +static void +mve_encode_rqq (unsigned bit28, unsigned size) +{ + inst.instruction |= bit28 << 28; + inst.instruction |= neon_logbits (size) << 20; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= inst.operands[0].reg << 12; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= HI1 (inst.operands[2].reg) << 5; + inst.instruction |= LOW4 (inst.operands[2].reg); + inst.is_neon = 1; +} + /* Encode insns with bit pattern: |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0| @@ -15884,6 +15939,65 @@ do_neon_qdmulh (void) } static void +do_mve_vabav (void) +{ + enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); + + if (rs == NS_NULL) + return; + + if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) + return; + + struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8 + | N_S16 | N_S32 | N_U8 | N_U16 + | N_U32); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + mve_encode_rqq (et.type == NT_unsigned, et.size); +} + +static void +do_mve_vmladav (void) +{ + enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL); + struct neon_type_el et = neon_check_type (3, rs, + N_EQK, N_EQK, N_SU_MVE | N_KEY); + + if (et.type == NT_unsigned + && (inst.instruction == M_MNEM_vmladavx + || inst.instruction == M_MNEM_vmladavax + || inst.instruction == M_MNEM_vmlsdav + || inst.instruction == M_MNEM_vmlsdava + || inst.instruction == M_MNEM_vmlsdavx + || inst.instruction == M_MNEM_vmlsdavax)) + first_error (BAD_SIMD_TYPE); + + constraint (inst.operands[2].reg > 14, + _("MVE vector register in the range [Q0..Q7] expected")); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + if (inst.instruction == M_MNEM_vmlsdav + || inst.instruction == M_MNEM_vmlsdava + || inst.instruction == M_MNEM_vmlsdavx + || inst.instruction == M_MNEM_vmlsdavax) + inst.instruction |= (et.size == 8) << 28; + else + inst.instruction |= (et.size == 8) << 8; + + mve_encode_rqq (et.type == NT_unsigned, 64); + inst.instruction |= (et.size == 32) << 16; +} + +static void do_neon_qrdmlah (void) { /* Check we're on the correct architecture. */ @@ -20573,7 +20687,7 @@ static struct asm_barrier_opt barrier_opt_names[] = /* */ #define mCEF(mnem, op, nops, ops, enc) \ - { #mnem, OPS##nops ops, OT_csuffixF, 0, M_MNEM##op, \ + { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \ ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 } @@ -22633,6 +22747,19 @@ static const struct asm_opcode insns[] = ToC("vpsteet", fe716f4d, 0, (), mve_vpt), ToC("vpsteee", fe712f4d, 0, (), mve_vpt), + /* MVE and MVE FP only. */ + mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav), + mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav), + mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav), + mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav), + mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav), + mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav), + mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav), + mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav), + mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav), + mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav), + mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav), + #undef ARM_VARIANT #define ARM_VARIANT & fpu_vfp_ext_v1xd #undef THUMB_VARIANT diff --git a/gas/testsuite/gas/arm/mve-vabav-bad.d b/gas/testsuite/gas/arm/mve-vabav-bad.d new file mode 100644 index 0000000..42c9dad --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vabav-bad.d @@ -0,0 +1,6 @@ +#name: bad MVE VABAV instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vabav-bad.l + +.*: +file format .*arm.* + diff --git a/gas/testsuite/gas/arm/mve-vabav-bad.l b/gas/testsuite/gas/arm/mve-vabav-bad.l new file mode 100644 index 0000000..40d4483 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vabav-bad.l @@ -0,0 +1,18 @@ +[^:]*: Assembler messages: +[^:]*:13: Error: bad type in SIMD instruction -- `vabav.s64 r0,q0,q1' +[^:]*:14: Error: bad type in SIMD instruction -- `vabav.f16 r0,q0,q1' +[^:]*:15: Error: bad type in SIMD instruction -- `vabav.f32 r0,q0,q1' +[^:]*:16: Error: bad type in SIMD instruction -- `vabav.p8 r0,q0,q1' +[^:]*:17: Error: bad type in SIMD instruction -- `vabav.p16 r0,q0,q1' +[^:]*:18: Error: r13 not allowed here -- `vabav.s32 r13,q0,q1' +[^:]*:19: Error: r15 not allowed here -- `vabav.s32 r15,q0,q1' +[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:22: Error: syntax error -- `vabaveq.s32 r0,q0,q1' +[^:]*:23: Error: syntax error -- `vabaveq.s32 r0,q0,q1' +[^:]*:25: Error: vector predicated instruction should be in VPT/VPST block -- `vabavt.s32 r0,q0,q1' +[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vabavt.s32 r0,q0,q1' diff --git a/gas/testsuite/gas/arm/mve-vabav-bad.s b/gas/testsuite/gas/arm/mve-vabav-bad.s new file mode 100644 index 0000000..dfb8dee --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vabav-bad.s @@ -0,0 +1,26 @@ +.macro cond op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s32 r0, q0, q1 +.endr +.endm + + + +.syntax unified +.text +.thumb +vabav.s64 r0, q0, q1 +vabav.f16 r0, q0, q1 +vabav.f32 r0, q0, q1 +vabav.p8 r0, q0, q1 +vabav.p16 r0, q0, q1 +vabav.s32 r13, q0, q1 +vabav.s32 r15, q0, q1 +cond vabav +vpst +vabaveq.s32 r0, q0, q1 +vabaveq.s32 r0, q0, q1 +it eq +vabavt.s32 r0, q0, q1 +vabavt.s32 r0, q0, q1 diff --git a/gas/testsuite/gas/arm/mve-vmladav-bad.d b/gas/testsuite/gas/arm/mve-vmladav-bad.d new file mode 100644 index 0000000..eb82d47 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmladav-bad.d @@ -0,0 +1,5 @@ +#name: Bad MVE VMLADAV instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vmladav-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmladav-bad.l b/gas/testsuite/gas/arm/mve-vmladav-bad.l new file mode 100644 index 0000000..fae770c --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmladav-bad.l @@ -0,0 +1,55 @@ +[^:]*: Assembler messages: +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Error: bad type in SIMD instruction -- `vmladav.s64 r0,q1,q2' +[^:]*:15: Error: bad type in SIMD instruction -- `vmladav.f32 r0,q1,q2' +[^:]*:16: Error: bad type in SIMD instruction -- `vmladava.s64 r0,q1,q2' +[^:]*:17: Error: bad type in SIMD instruction -- `vmladava.f32 r0,q1,q2' +[^:]*:18: Error: bad type in SIMD instruction -- `vmladavx.s64 r0,q1,q2' +[^:]*:19: Error: bad type in SIMD instruction -- `vmladavx.f32 r0,q1,q2' +[^:]*:20: Error: bad type in SIMD instruction -- `vmladavax.s64 r0,q1,q2' +[^:]*:21: Error: bad type in SIMD instruction -- `vmladavax.f32 r0,q1,q2' +[^:]*:22: Error: bad type in SIMD instruction -- `vmladavx.u32 r0,q1,q2' +[^:]*:23: Error: bad type in SIMD instruction -- `vmladavax.u16 r0,q1,q2' +[^:]*:25: Error: syntax error -- `vmladaveq.s32 r0,q1,q2' +[^:]*:26: Error: syntax error -- `vmladaveq.s32 r0,q1,q2' +[^:]*:28: Error: syntax error -- `vmladaveq.s32 r0,q1,q2' +[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavt.s32 r0,q1,q2' +[^:]*:31: Error: instruction missing MVE vector predication code -- `vmladav.s32 r0,q1,q2' +[^:]*:33: Error: syntax error -- `vmladavaeq.s32 r0,q1,q2' +[^:]*:34: Error: syntax error -- `vmladavaeq.s32 r0,q1,q2' +[^:]*:36: Error: syntax error -- `vmladavaeq.s32 r0,q1,q2' +[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavat.s32 r0,q1,q2' +[^:]*:39: Error: instruction missing MVE vector predication code -- `vmladava.s32 r0,q1,q2' +[^:]*:41: Error: syntax error -- `vmladavxeq.s32 r0,q1,q2' +[^:]*:42: Error: syntax error -- `vmladavxeq.s32 r0,q1,q2' +[^:]*:44: Error: syntax error -- `vmladavxeq.s32 r0,q1,q2' +[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavxt.s32 r0,q1,q2' +[^:]*:47: Error: instruction missing MVE vector predication code -- `vmladavx.s32 r0,q1,q2' +[^:]*:49: Error: syntax error -- `vmladavaxeq.s32 r0,q1,q2' +[^:]*:50: Error: syntax error -- `vmladavaxeq.s32 r0,q1,q2' +[^:]*:52: Error: syntax error -- `vmladavaxeq.s32 r0,q1,q2' +[^:]*:53: Error: vector predicated instruction should be in VPT/VPST block -- `vmladavaxt.s32 r0,q1,q2' +[^:]*:55: Error: instruction missing MVE vector predication code -- `vmladavax.s32 r0,q1,q2' diff --git a/gas/testsuite/gas/arm/mve-vmladav-bad.s b/gas/testsuite/gas/arm/mve-vmladav-bad.s new file mode 100644 index 0000000..6621372 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmladav-bad.s @@ -0,0 +1,55 @@ +.macro cond, op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s16 r0, q1, q2 +.endr +.endm + +.syntax unified +.thumb +cond vmladav +cond vmladava +cond vmladavx +cond vmladavax +vmladav.s64 r0, q1, q2 +vmladav.f32 r0, q1, q2 +vmladava.s64 r0, q1, q2 +vmladava.f32 r0, q1, q2 +vmladavx.s64 r0, q1, q2 +vmladavx.f32 r0, q1, q2 +vmladavax.s64 r0, q1, q2 +vmladavax.f32 r0, q1, q2 +vmladavx.u32 r0, q1, q2 +vmladavax.u16 r0, q1, q2 +it eq +vmladaveq.s32 r0, q1, q2 +vmladaveq.s32 r0, q1, q2 +vpst +vmladaveq.s32 r0, q1, q2 +vmladavt.s32 r0, q1, q2 +vpst +vmladav.s32 r0, q1, q2 +it eq +vmladavaeq.s32 r0, q1, q2 +vmladavaeq.s32 r0, q1, q2 +vpst +vmladavaeq.s32 r0, q1, q2 +vmladavat.s32 r0, q1, q2 +vpst +vmladava.s32 r0, q1, q2 +it eq +vmladavxeq.s32 r0, q1, q2 +vmladavxeq.s32 r0, q1, q2 +vpst +vmladavxeq.s32 r0, q1, q2 +vmladavxt.s32 r0, q1, q2 +vpst +vmladavx.s32 r0, q1, q2 +it eq +vmladavaxeq.s32 r0, q1, q2 +vmladavaxeq.s32 r0, q1, q2 +vpst +vmladavaxeq.s32 r0, q1, q2 +vmladavaxt.s32 r0, q1, q2 +vpst +vmladavax.s32 r0, q1, q2 diff --git a/gas/testsuite/gas/arm/mve-vmlav-bad.d b/gas/testsuite/gas/arm/mve-vmlav-bad.d new file mode 100644 index 0000000..6b6af1b --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlav-bad.d @@ -0,0 +1,5 @@ +#name: Bad MVE VMLAV instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vmlav-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmlav-bad.l b/gas/testsuite/gas/arm/mve-vmlav-bad.l new file mode 100644 index 0000000..018a8fb --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlav-bad.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:10: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:11: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Error: bad type in SIMD instruction -- `vmlav.s64 r0,q1,q2' +[^:]*:13: Error: bad type in SIMD instruction -- `vmlav.f32 r0,q1,q2' +[^:]*:14: Error: bad type in SIMD instruction -- `vmlava.s64 r0,q1,q2' +[^:]*:15: Error: bad type in SIMD instruction -- `vmlava.f32 r0,q1,q2' +[^:]*:16: Error: bad instruction `vmlavx.s32 r0,q1,q2' +[^:]*:17: Error: bad instruction `vmlavax.s32 r0,q1,q2' +[^:]*:19: Error: syntax error -- `vmlaveq.s32 r0,q1,q2' +[^:]*:20: Error: syntax error -- `vmlaveq.s32 r0,q1,q2' +[^:]*:22: Error: syntax error -- `vmlaveq.s32 r0,q1,q2' +[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vmlavt.s32 r0,q1,q2' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vmlav.s32 r0,q1,q2' +[^:]*:27: Error: syntax error -- `vmlavaeq.s32 r0,q1,q2' +[^:]*:28: Error: syntax error -- `vmlavaeq.s32 r0,q1,q2' +[^:]*:30: Error: syntax error -- `vmlavaeq.s32 r0,q1,q2' +[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vmlavat.s32 r0,q1,q2' +[^:]*:33: Error: instruction missing MVE vector predication code -- `vmlava.s32 r0,q1,q2' diff --git a/gas/testsuite/gas/arm/mve-vmlav-bad.s b/gas/testsuite/gas/arm/mve-vmlav-bad.s new file mode 100644 index 0000000..1359636 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlav-bad.s @@ -0,0 +1,33 @@ +.macro cond, op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s16 r0, q1, q2 +.endr +.endm + +.syntax unified +.thumb +cond vmlav +cond vmlava +vmlav.s64 r0, q1, q2 +vmlav.f32 r0, q1, q2 +vmlava.s64 r0, q1, q2 +vmlava.f32 r0, q1, q2 +vmlavx.s32 r0, q1, q2 +vmlavax.s32 r0, q1, q2 +it eq +vmlaveq.s32 r0, q1, q2 +vmlaveq.s32 r0, q1, q2 +vpst +vmlaveq.s32 r0, q1, q2 +vmlavt.s32 r0, q1, q2 +vpst +vmlav.s32 r0, q1, q2 +it eq +vmlavaeq.s32 r0, q1, q2 +vmlavaeq.s32 r0, q1, q2 +vpst +vmlavaeq.s32 r0, q1, q2 +vmlavat.s32 r0, q1, q2 +vpst +vmlava.s32 r0, q1, q2 diff --git a/gas/testsuite/gas/arm/mve-vmlsdav-bad.d b/gas/testsuite/gas/arm/mve-vmlsdav-bad.d new file mode 100644 index 0000000..cdcaae9 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlsdav-bad.d @@ -0,0 +1,5 @@ +#name: Bad MVE VMLSDAV instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vmlsdav-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmlsdav-bad.l b/gas/testsuite/gas/arm/mve-vmlsdav-bad.l new file mode 100644 index 0000000..f627053 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlsdav-bad.l @@ -0,0 +1,47 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: Odd register not allowed here -- `vmlsdav.s16 r1,q1,q2' +[^:]*:11: Error: bad type in SIMD instruction -- `vmlsdav.u16 r0,q1,q2' +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:13: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:15: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2' +[^:]*:18: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2' +[^:]*:20: Error: syntax error -- `vmlsdaveq.s16 r0,q1,q2' +[^:]*:21: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavt.s16 r0,q1,q2' +[^:]*:23: Error: instruction missing MVE vector predication code -- `vmlsdav.s16 r0,q1,q2' +[^:]*:25: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2' +[^:]*:26: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2' +[^:]*:28: Error: syntax error -- `vmlsdavaeq.s16 r0,q1,q2' +[^:]*:29: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavat.s16 r0,q1,q2' +[^:]*:31: Error: instruction missing MVE vector predication code -- `vmlsdava.s16 r0,q1,q2' +[^:]*:33: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2' +[^:]*:34: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2' +[^:]*:36: Error: syntax error -- `vmlsdavxeq.s16 r0,q1,q2' +[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavxt.s16 r0,q1,q2' +[^:]*:39: Error: instruction missing MVE vector predication code -- `vmlsdavx.s16 r0,q1,q2' +[^:]*:41: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2' +[^:]*:42: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2' +[^:]*:44: Error: syntax error -- `vmlsdavaxeq.s16 r0,q1,q2' +[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vmlsdavaxt.s16 r0,q1,q2' +[^:]*:47: Error: instruction missing MVE vector predication code -- `vmlsdavax.s16 r0,q1,q2' diff --git a/gas/testsuite/gas/arm/mve-vmlsdav-bad.s b/gas/testsuite/gas/arm/mve-vmlsdav-bad.s new file mode 100644 index 0000000..c955a0d --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlsdav-bad.s @@ -0,0 +1,47 @@ +.macro cond, op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().s16 r0, q1, q2 +.endr +.endm + +.syntax unified +.thumb +vmlsdav.s16 r1, q1, q2 +vmlsdav.u16 r0, q1, q2 +cond vmlsdav +cond vmlsdava +cond vmlsdavx +cond vmlsdavax +it eq +vmlsdaveq.s16 r0, q1, q2 +vmlsdaveq.s16 r0, q1, q2 +vpst +vmlsdaveq.s16 r0, q1, q2 +vmlsdavt.s16 r0, q1, q2 +vpst +vmlsdav.s16 r0, q1, q2 +it eq +vmlsdavaeq.s16 r0, q1, q2 +vmlsdavaeq.s16 r0, q1, q2 +vpst +vmlsdavaeq.s16 r0, q1, q2 +vmlsdavat.s16 r0, q1, q2 +vpst +vmlsdava.s16 r0, q1, q2 +it eq +vmlsdavxeq.s16 r0, q1, q2 +vmlsdavxeq.s16 r0, q1, q2 +vpst +vmlsdavxeq.s16 r0, q1, q2 +vmlsdavxt.s16 r0, q1, q2 +vpst +vmlsdavx.s16 r0, q1, q2 +it eq +vmlsdavaxeq.s16 r0, q1, q2 +vmlsdavaxeq.s16 r0, q1, q2 +vpst +vmlsdavaxeq.s16 r0, q1, q2 +vmlsdavaxt.s16 r0, q1, q2 +vpst +vmlsdavax.s16 r0, q1, q2