From: Siddhesh Poyarekar Date: Mon, 23 Oct 2017 14:52:42 +0000 (+0530) Subject: aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat X-Git-Tag: upstream/2.30~2301 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a2e0a7f12ba57a49d1380c7ba1ff4b1f51d67347;p=platform%2Fupstream%2Fglibc.git aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the ctr_el0 register, which tells us the minimum observable cache line size by userspace. This typically is the same as the L1 cache line size, but that may not always be true. It could be a higher level cache line size as long as cache cleaning and invalidation work correctly with that line size in userspace. The falkor core for example reports the L2 line size as the dcache line size in CTR_EL0 while also reporting the correct L1 dcache line size via CCSIDR_EL1. * manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat. Reviewed-by: Rical Jasan Reviewed-by: Szabolcs Nagy --- diff --git a/ChangeLog b/ChangeLog index 8904437..b756f97 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,8 @@ 2017-10-23 Siddhesh Poyarekar + * manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE, + _SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat. + * manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE, _SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE, _SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC, diff --git a/manual/conf.texi b/manual/conf.texi index 079bdb2..62ab444 100644 --- a/manual/conf.texi +++ b/manual/conf.texi @@ -690,6 +690,12 @@ Inquire about the associativity of the Level 1 instruction cache. @standards{GNU, unistd.h} Inquire about the line length of the Level 1 instruction cache. +On aarch64, the cache line size returned is the minimum instruction cache line +size observable by userspace. This is typically the same as the L1 icache +size but on some cores it may not be so. However, it is specified in the +architecture that operations such as cache line invalidation are consistent +with the size reported with this variable. + @item _SC_LEVEL1_DCACHE_SIZE @standards{GNU, unistd.h} Inquire about the size of the Level 1 data cache. @@ -702,6 +708,12 @@ Inquire about the associativity of the Level 1 data cache. @standards{GNU, unistd.h} Inquire about the line length of the Level 1 data cache. +On aarch64, the cache line size returned is the minimum data cache line size +observable by userspace. This is typically the same as the L1 dcache size but +on some cores it may not be so. However, it is specified in the architecture +that operations such as cache line invalidation are consistent with the size +reported with this variable. + @item _SC_LEVEL2_CACHE_SIZE @standards{GNU, unistd.h} Inquire about the size of the Level 2 cache.