From: Stephen Boyd <sboyd@codeaurora.org>
Date: Sat, 27 Jan 2018 00:41:52 +0000 (-0800)
Subject: Merge branches 'clk-at91', 'clk-imx7ulp', 'clk-axigen', 'clk-si5351' and 'clk-pxa... 
X-Git-Tag: v4.19~1676^2~4
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a2c09c12d4e1935807d02d58d2a338fa74554305;p=platform%2Fkernel%2Flinux-rpi.git

Merge branches 'clk-at91', 'clk-imx7ulp', 'clk-axigen', 'clk-si5351' and 'clk-pxa' into clk-next

* clk-at91:
  clk: at91: pmc: Support backup for programmable clocks
  clk: at91: pmc: Save SCSR during suspend
  clk: at91: pmc: Wait for clocks when resuming

* clk-imx7ulp:
  clk: Don't touch hardware when reparenting during registration

* clk-axigen:
  clk: axi-clkgen: Round closest in round_rate() and recalc_rate()
  clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()

* clk-si5351:
  clk: si5351: _si5351_clkout_reset_pll() can be static
  clk: si5351: Do not enable parent clocks on probe
  clk: si5351: Rename internal plls to avoid name collisions
  clk: si5351: Apply PLL soft reset before enabling the outputs
  clk: si5351: Add DT property to enable PLL reset
  clk: si5351: implement remove handler

* clk-pxa:
  clk: pxa: unbreak lookup of CLK_POUT
---

a2c09c12d4e1935807d02d58d2a338fa74554305
diff --cc drivers/clk/clk.c
index 3526bc0,647d056,999777a,647d056,647d056,647d056..5ec5809
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@@@@@@ -1077,58 -934,15 -934,15 -934,15 -934,15 -934,15 +1077,58 @@@@@@@ static int clk_core_determine_round_nol
      			return rate;
      
      		req->rate = rate;
 -----	} else if (core->flags & CLK_SET_RATE_PARENT) {
 -----		return clk_core_round_rate_nolock(parent, req);
      	} else {
 -----		req->rate = core->rate;
 +++++		return -EINVAL;
  +   	}
  +   
  +   	return 0;
  +   }
  +   
 +++++static void clk_core_init_rate_req(struct clk_core * const core,
 +++++				   struct clk_rate_request *req)
 +++++{
 +++++	struct clk_core *parent;
 +++++
 +++++	if (WARN_ON(!core || !req))
 +++++		return;
 +++++
 +++++	parent = core->parent;
 +++++	if (parent) {
 +++++		req->best_parent_hw = parent->hw;
 +++++		req->best_parent_rate = parent->rate;
 +++++	} else {
 +++++		req->best_parent_hw = NULL;
 +++++		req->best_parent_rate = 0;
 + +++	}
 +++++}
 + +++
 +++++static bool clk_core_can_round(struct clk_core * const core)
 +++++{
 +++++	if (core->ops->determine_rate || core->ops->round_rate)
 +++++		return true;
 +++++
 +++++	return false;
 +++++}
 +++++
 +++++static int clk_core_round_rate_nolock(struct clk_core *core,
 +++++				      struct clk_rate_request *req)
 +++++{
 +++++	lockdep_assert_held(&prepare_lock);
 +++++
 +++++	if (!core)
 +++++		return 0;
 +++++
 +++++	clk_core_init_rate_req(core, req);
 +++++
 +++++	if (clk_core_can_round(core))
 +++++		return clk_core_determine_round_nolock(core, req);
 +++++	else if (core->flags & CLK_SET_RATE_PARENT)
 +++++		return clk_core_round_rate_nolock(core->parent, req);
 +++++
 +++++	req->rate = core->rate;
 + +++	return 0;
 + +++}
 + +++
      /**
       * __clk_determine_rate - get the closest rate actually supported by a clock
       * @hw: determine the rate of this clock
@@@@@@@ -2341,13 -2000,15 -2000,15 -2000,15 -2000,15 -2000,15 +2341,13 @@@@@@@ int clk_set_phase(struct clk *clk, int 
      
      	clk_prepare_lock();
      
 -----	trace_clk_set_phase(clk->core, degrees);
  -   
  -   	if (clk->core->ops->set_phase)
  -   		ret = clk->core->ops->set_phase(clk->core->hw, degrees);
 +++++	if (clk->exclusive_count)
 +++++		clk_core_rate_unprotect(clk->core);
      
 - ---	if (clk->core->ops->set_phase)
 - ---		ret = clk->core->ops->set_phase(clk->core->hw, degrees);
  -   	trace_clk_set_phase_complete(clk->core, degrees);
 +++++	ret = clk_core_set_phase_nolock(clk->core, degrees);
      
 - ---	trace_clk_set_phase_complete(clk->core, degrees);
 - ---
 -----	if (!ret)
 -----		clk->core->phase = degrees;
 +++++	if (clk->exclusive_count)
 +++++		clk_core_rate_protect(clk->core);
      
      	clk_prepare_unlock();