From: Evgeny Leviant <eleviant@accesssoftek.com>
Date: Mon, 26 Oct 2020 19:31:41 +0000 (+0300)
Subject: [ARM][SchedModels] Move IsLDMBaseRegInListPred to ARMSchedule.td. NFC
X-Git-Tag: llvmorg-13-init~8130
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a28388f95beb029241b4ab221b279698a5559f82;p=platform%2Fupstream%2Fllvm.git

[ARM][SchedModels] Move IsLDMBaseRegInListPred to ARMSchedule.td. NFC

This predicate is not specific to cortex-a57 and can be used in other processor
models as well.
---

diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td
index 81fb6a3..5838e72 100644
--- a/llvm/lib/Target/ARM/ARMSchedule.td
+++ b/llvm/lib/Target/ARM/ARMSchedule.td
@@ -185,6 +185,10 @@ def IsLDMBaseRegInList : CheckFunctionPredicate<
 let FunctionMapper = "ARM_AM::getAM3Op" in {
   class CheckAM3OpSub<int n> : CheckImmOperand_s<n, "ARM_AM::sub"> {}
 }
+
+// LDM, base reg in list
+def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td
index 3485c7f..9a541e1 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA57.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA57.td
@@ -63,9 +63,6 @@ def IsLdstsoMinusRegPredX0 : MCSchedPredicate<CheckAM2OpSub<2>>;
 def IsLdstsoMinusRegPred : MCSchedPredicate<CheckAM2OpSub<3>>;
 def IsLdstsoMinusRegPredX2 : MCSchedPredicate<CheckAM2OpSub<4>>;
 
-// LDM, base reg in list
-def IsLDMBaseRegInListPred : MCSchedPredicate<IsLDMBaseRegInList>;
-
 class A57WriteLMOpsListType<list<SchedWriteRes> writes> {
   list <SchedWriteRes> Writes = writes;
   SchedMachineModel SchedModel = ?;