From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date: Sun, 5 Mar 2023 21:12:36 +0000 (+0200)
Subject: nir: fix nir_ishl_imm
X-Git-Tag: upstream/23.3.3~12038
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a278eeb71974a89b6dd7c0fa3dbfe97183aeb657;p=platform%2Fupstream%2Fmesa.git

nir: fix nir_ishl_imm

Both GLSL & SPIRV have undefined values for shift > bitsize. But SM5
says :

   "This instruction performs a component-wise shift of each 32-bit
    value in src0 left by an unsigned integer bit count provided by
    the LSB 5 bits (0-31 range) in src1, inserting 0."

Better to not hard code the wrong behavior in NIR.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e227bb9fd5 ("nir/builder: add ishl_imm helper")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@colllabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21720>
---

diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index d92583f..83b2b6e 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -841,9 +841,8 @@ nir_ishl_imm(nir_builder *build, nir_ssa_def *x, uint32_t y)
 {
    if (y == 0) {
       return x;
-   } else if (y >= x->bit_size) {
-      return nir_imm_intN_t(build, 0, x->bit_size);
    } else {
+      assert (y < x->bit_size);
       return nir_ishl(build, x, nir_imm_int(build, y));
    }
 }