From: Andre Przywara <andre.przywara@arm.com>
Date: Thu, 17 Mar 2022 16:23:44 +0000 (+0000)
Subject: ARM: dts: suniv: F1C100: fix timer node
X-Git-Tag: v6.1-rc5~1259^2~14^2~8
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a26123f355f23d8ba980d7ecf4899d309d5cd708;p=platform%2Fkernel%2Flinux-starfive.git

ARM: dts: suniv: F1C100: fix timer node

The Allwinner F1C100s has three timer instances, each with their own
interrupt line.

Add the missing two interrupts to the DT node, to match the DT binding.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220317162349.739636-8-andre.przywara@arm.com
---

diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 0a7fa37..f455e27 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -105,7 +105,7 @@
 		timer@1c20c00 {
 			compatible = "allwinner,suniv-f1c100s-timer";
 			reg = <0x01c20c00 0x90>;
-			interrupts = <13>;
+			interrupts = <13>, <14>, <15>;
 			clocks = <&osc24M>;
 		};