From: Adam Nemet <anemet@caviumnetworks.com>
Date: Thu, 6 Nov 2008 19:49:26 +0000 (+0000)
Subject: 	* config/tc-mips.c (COP_INSN): Change logic to always return false
X-Git-Tag: sid-snapshot-20081201~205
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a242dc0d23ddab8b648547e661591fc18e84c69c;p=external%2Fbinutils.git

	* config/tc-mips.c (COP_INSN): Change logic to always return false
	for FP instructions.

testsuite/
	* gas/mips/mips1-fp.s, testsuite/gas/mips/mips1-fp.d,
	testsuite/gas/mips/mips1-fp.l: New tests.
	* gas/mips/mips.exp: Run them.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8bb6dab..c89a192 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2008-11-06  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* config/tc-mips.c (COP_INSN): Change logic to always return false
+	for FP instructions.
+
 2008-11-06  Chao-ying Fu  <fu@mips.com>
 
 	* config/tc-mips.c (validate_mips_insn): Add case '1'.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index cc900c3..17ee8d1 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -514,12 +514,11 @@ static int mips_32bitmode = 0;
 /* Returns true for a (non floating-point) coprocessor instruction.  Reading
    or writing the condition code is only possible on the coprocessors and
    these insns are not marked with INSN_COP.  Thus for these insns use the
-   condition-code flags unless this is the floating-point coprocessor.  */
+   condition-code flags.  */
 #define COP_INSN(PINFO)							\
   (PINFO != INSN_MACRO							\
-   && (((PINFO) & INSN_COP)						\
-       || ((PINFO) & (INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)	\
-	   && ((PINFO) & (FP_S | FP_D)) == 0)))
+   && ((PINFO) & (FP_S | FP_D)) == 0					\
+   && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
 
 /* MIPS PIC level.  */
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 7fec932..dbe5cb8 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2008-11-06  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* gas/mips/mips1-fp.s, testsuite/gas/mips/mips1-fp.d,
+	testsuite/gas/mips/mips1-fp.l: New tests.
+	* gas/mips/mips.exp: Run them.
+
 2008-11-06  Chao-ying Fu  <fu@mips.com>
 
 	* gas/mips/mips32-sync.d, gas/mip/mips32-sync.s: New tests.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index f1445bc..0dc6017 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -398,6 +398,9 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "abs"		[mips_arch_list_matching mips1]
     run_dump_test_arches "add"		[mips_arch_list_matching mips1]
     run_dump_test_arches "and"		[mips_arch_list_matching mips1]
+    run_dump_test_arches "mips1-fp"	[mips_arch_list_matching mips1]
+    run_list_test_arches "mips1-fp" "-32 -msoft-float" \
+					[mips_arch_list_matching mips1]
     run_dump_test "break20"
     run_dump_test "trap20"
 
diff --git a/gas/testsuite/gas/mips/mips1-fp.d b/gas/testsuite/gas/mips/mips1-fp.d
new file mode 100644
index 0000000..a681a30
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips1-fp.d
@@ -0,0 +1,12 @@
+#as: -32
+#objdump: -M reg-names=numeric -dr
+#name: MIPS1 FP instructions
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <foo>:
+.*:	46041000 	add.s	\$f0,\$f2,\$f4
+.*:	44420000 	cfc1	\$2,\$0
+#pass
diff --git a/gas/testsuite/gas/mips/mips1-fp.l b/gas/testsuite/gas/mips/mips1-fp.l
new file mode 100644
index 0000000..72ed043
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips1-fp.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f0,\$f2,\$f4'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `cfc1 \$2,\$0'
diff --git a/gas/testsuite/gas/mips/mips1-fp.s b/gas/testsuite/gas/mips/mips1-fp.s
new file mode 100644
index 0000000..0c71761
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips1-fp.s
@@ -0,0 +1,7 @@
+# Source file used to test -mips1 fp instructions.
+
+# This is not a complete list of mips1 FP instructions.
+
+foo:
+	add.s	$f0,$f2,$f4
+	cfc1	$2,$0