From: Alexander Soldatov <soldatov.a@samsung.com>
Date: Wed, 12 Jul 2023 21:35:22 +0000 (+0300)
Subject: [RISC-V] Missing defines in GC (#88661)
X-Git-Tag: accepted/tizen/unified/riscv/20231226.055536~1109
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a23c7a19076177d85e4a03a889aa9567db41d52a;p=platform%2Fupstream%2Fdotnet%2Fruntime.git

[RISC-V] Missing defines in GC (#88661)
---

diff --git a/src/coreclr/gc/env/gcenv.interlocked.inl b/src/coreclr/gc/env/gcenv.interlocked.inl
index 136348b..3e4d761 100644
--- a/src/coreclr/gc/env/gcenv.interlocked.inl
+++ b/src/coreclr/gc/env/gcenv.interlocked.inl
@@ -13,7 +13,7 @@
 #ifndef _MSC_VER
 __forceinline void Interlocked::InterlockedOperationBarrier()
 {
-#if defined(HOST_ARM64) || defined(HOST_LOONGARCH64)
+#if defined(HOST_ARM64) || defined(HOST_LOONGARCH64) || defined(HOST_RISCV64)
     // See PAL_InterlockedOperationBarrier() in the PAL
     __sync_synchronize();
 #endif
diff --git a/src/coreclr/gc/gc.cpp b/src/coreclr/gc/gc.cpp
index cd1736a..14af5f3 100644
--- a/src/coreclr/gc/gc.cpp
+++ b/src/coreclr/gc/gc.cpp
@@ -26240,7 +26240,7 @@ void gc_heap::save_post_plug_info (uint8_t* last_pinned_plug, uint8_t* last_obje
 }
 
 // enable on processors known to have a useful prefetch instruction
-#if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM64)
+#if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM64) || defined(TARGET_RISCV64)
 #define PREFETCH
 #endif
 
diff --git a/src/coreclr/gc/unix/gcenv.unix.cpp b/src/coreclr/gc/unix/gcenv.unix.cpp
index a024d3f..285b783 100644
--- a/src/coreclr/gc/unix/gcenv.unix.cpp
+++ b/src/coreclr/gc/unix/gcenv.unix.cpp
@@ -136,7 +136,7 @@ typedef cpuset_t cpu_set_t;
 #endif
 #endif // __APPLE__
 
-#if defined(HOST_ARM) || defined(HOST_ARM64) || defined(HOST_LOONGARCH64)
+#if defined(HOST_ARM) || defined(HOST_ARM64) || defined(HOST_LOONGARCH64) || defined(HOST_RISCV64)
 #define SYSCONF_GET_NUMPROCS _SC_NPROCESSORS_CONF
 #else
 #define SYSCONF_GET_NUMPROCS _SC_NPROCESSORS_ONLN