From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Thu, 17 May 2018 00:30:04 +0000 (-0700)
Subject: intel/fs: Assert that the gen4-6 plane restrictions are followed
X-Git-Tag: upstream/19.0.0~4890
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a1a850cd3411400ce832e77c4be1f0e14924ce9e;p=platform%2Fupstream%2Fmesa.git

intel/fs: Assert that the gen4-6 plane restrictions are followed

The fall-back does not work correctly in SIMD16 mode and the register
allocator should ensure that we never hit this case anyway.

Reviewed-by: Matt Turner <mattst88@gmail.com>
---

diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 6d5306a..0c050a7 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -817,8 +817,14 @@ fs_generator::generate_linterp(fs_inst *inst,
       }
 
       return true;
-   } else if (devinfo->has_pln &&
-              (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
+   } else if (devinfo->has_pln) {
+      /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
+       *
+       *    "[DevSNB]:<src1> must be even register aligned.
+       *
+       * This restriction is lifted on Ivy Bridge.
+       */
+      assert(devinfo->gen >= 7 || (delta_x.nr & 1) == 0);
       brw_PLN(p, dst, interp, delta_x);
 
       return false;