From: Priyanka Singh <priyanka.singh@nxp.com>
Date: Thu, 19 Aug 2021 06:09:01 +0000 (+0530)
Subject: drivers: ddr: util.c: Fix divide by zero issue
X-Git-Tag: v2022.01~50^2~61
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a1932ece70e1441b169650d475d7814920a94c27;p=platform%2Fkernel%2Fu-boot.git

drivers: ddr: util.c: Fix divide by zero issue

Fix possible divide by zero issue in get_memory_clk_period_ps
by adding a check

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---

diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index ac4f8d2..43cb018 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -75,10 +76,13 @@ unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num)
 
 	/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
 	unsigned long long rem, mclk_ps = ULL_2E12;
-
-	/* Now perform the big divide, the result fits in 32-bits */
-	rem = do_div(mclk_ps, data_rate);
-	result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+	if (data_rate) {
+		/* Now perform the big divide, the result fits in 32-bits */
+		rem = do_div(mclk_ps, data_rate);
+		result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+	} else {
+		result = 0;
+	}
 
 	return result;
 }