From: Samin Guo <samin.guo@starfivetech.com>
Date: Wed, 23 Aug 2023 02:43:54 +0000 (+0800)
Subject: riscv: dts: starfive: jh7110: add dma-coherent for vpu/jpu
X-Git-Tag: accepted/tizen/unified/riscv/20231013.094029~4
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a0668cbec05e6403fd028c9bfe813e66a9edff68;p=platform%2Fkernel%2Flinux-starfive.git

riscv: dts: starfive: jh7110: add dma-coherent for vpu/jpu

Use DMA-Coherent to avoid DIRECT_REMAP when allocating DMA
buffers

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>

[sw0312.kim: cherry-pick the commit dfb44f0122ba from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

Change-Id: Ia0d3955010e963c0fb635e10081c1a2ab31155d4
---

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index c66f130adc1f..d24ed3b113f7 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -998,6 +998,7 @@
 
 		jpu: jpu@13090000 {
 			compatible = "starfive,jpu";
+			dma-coherent;
 			reg = <0x0 0x13090000 0x0 0x300>;
 			interrupts = <14>;
 			clocks = <&syscrg JH7110_SYSCLK_CODAJ12_AXI>,
@@ -1016,6 +1017,7 @@
 
 		vpu_dec: vpu_dec@130A0000 {
 			compatible = "starfive,vdec";
+			dma-coherent;
 			reg = <0x0 0x130A0000 0x0 0x10000>;
 			interrupts = <13>;
 			clocks = <&syscrg JH7110_SYSCLK_WAVE511_AXI>,
@@ -1039,6 +1041,7 @@
 
 		vpu_enc: vpu_enc@130B0000 {
 			compatible = "starfive,venc";
+			dma-coherent;
 			reg = <0x0 0x130B0000 0x0 0x10000>;
 			interrupts = <15>;
 			clocks = <&syscrg JH7110_SYSCLK_VENC_AXI>,