From: Fei Peng <fei.peng@intel.com>
Date: Wed, 11 Jul 2018 22:55:37 +0000 (-0700)
Subject: Fix VEX.vvvv encoding for AVX.BlendVariable
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=a03b08ab38186db8bb30a412bc73165810140119;p=platform%2Fupstream%2Fcoreclr.git

Fix VEX.vvvv encoding for AVX.BlendVariable
---

diff --git a/src/jit/emitxarch.cpp b/src/jit/emitxarch.cpp
index 7809c50e57..bdbf3356a9 100644
--- a/src/jit/emitxarch.cpp
+++ b/src/jit/emitxarch.cpp
@@ -293,6 +293,9 @@ bool emitter::IsDstDstSrcAVXInstruction(instruction ins)
         case INS_unpcklps:
         case INS_unpckhpd:
         case INS_unpcklpd:
+        case INS_vblendvps:
+        case INS_vblendvpd:
+        case INS_vpblendvb:
         case INS_vfmadd132pd:
         case INS_vfmadd213pd:
         case INS_vfmadd231pd:
@@ -9382,7 +9385,8 @@ BYTE* emitter::emitOutputAM(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
         {
             regNumber src1 = id->idReg2();
 
-            if ((id->idInsFmt() != IF_RWR_RRD_ARD) && (id->idInsFmt() != IF_RWR_RRD_ARD_CNS))
+            if ((id->idInsFmt() != IF_RWR_RRD_ARD) && (id->idInsFmt() != IF_RWR_RRD_ARD_CNS) &&
+                (id->idInsFmt() != IF_RWR_RRD_ARD_RRD))
             {
                 src1 = id->idReg1();
             }