From: uros Date: Sat, 29 Oct 2011 18:38:27 +0000 (+0000) Subject: * config/i386/i386.md (xop_sha3): Rename from xop_ashl3. X-Git-Tag: upstream/4.9.2~16680 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9f68982088705ec16e2a44b18f7bd99f6a96508d;p=platform%2Fupstream%2Flinaro-gcc.git * config/i386/i386.md (xop_sha3): Rename from xop_ashl3. Update all uses. (xop_shl3): Rename from xop_lshl3. Update all uses. * config/i386/i386.c: Update all uses. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@180659 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0e3ea11..4d7d8ff 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,12 @@ 2011-10-29 Uros Bizjak + * config/i386/i386.md (xop_sha3): Rename from xop_ashl3. + Update all uses. + (xop_shl3): Rename from xop_lshl3. Update all uses. + * config/i386/i386.c: Update all uses. + +2011-10-29 Uros Bizjak + * config/i386/i386.md (lshlv16qi3): Remove expander. (lshrv16qi3): New expander. (v16qi3): Macroize expander from ashrv16qi3 and lshrv16qi3 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index bb0433f..148fcfb 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -26538,14 +26538,14 @@ static const struct builtin_description bdesc_multi_arg[] = { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_ashlv16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI }, - { OPTION_MASK_ISA_XOP, CODE_FOR_xop_lshlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI }, + { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF }, { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF }, diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c5ef498..30262b0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -11253,7 +11253,7 @@ { rtx neg = gen_reg_rtx (mode); emit_insn (gen_neg2 (neg, operands[2])); - emit_insn (gen_xop_lshl3 (operands[0], operands[1], neg)); + emit_insn (gen_xop_shl3 (operands[0], operands[1], neg)); DONE; }) @@ -11268,7 +11268,7 @@ { rtx neg = gen_reg_rtx (mode); emit_insn (gen_neg2 (neg, operands[2])); - emit_insn (gen_xop_lshl3 (operands[0], operands[1], neg)); + emit_insn (gen_xop_shl3 (operands[0], operands[1], neg)); DONE; } }) @@ -11289,7 +11289,7 @@ { rtx neg = gen_reg_rtx (mode); emit_insn (gen_neg2 (neg, operands[2])); - emit_insn (gen_xop_ashl3 (operands[0], operands[1], neg)); + emit_insn (gen_xop_sha3 (operands[0], operands[1], neg)); DONE; }) @@ -11303,7 +11303,7 @@ { rtx neg = gen_reg_rtx (V4SImode); emit_insn (gen_negv4si2 (neg, operands[2])); - emit_insn (gen_xop_ashlv4si3 (operands[0], operands[1], neg)); + emit_insn (gen_xop_shav4si3 (operands[0], operands[1], neg)); DONE; } }) @@ -11321,7 +11321,7 @@ (match_operand:VI12_128 2 "nonimmediate_operand" "")))] "TARGET_XOP" { - emit_insn (gen_xop_ashl3 (operands[0], operands[1], operands[2])); + emit_insn (gen_xop_sha3 (operands[0], operands[1], operands[2])); DONE; }) @@ -11335,7 +11335,7 @@ if (!TARGET_AVX2) { operands[2] = force_reg (mode, operands[2]); - emit_insn (gen_xop_ashl3 (operands[0], operands[1], operands[2])); + emit_insn (gen_xop_sha3 (operands[0], operands[1], operands[2])); DONE; } }) @@ -11347,7 +11347,7 @@ (match_operand:VI48_256 2 "nonimmediate_operand" "")))] "TARGET_AVX2") -(define_insn "xop_ashl3" +(define_insn "xop_sha3" [(set (match_operand:VI_128 0 "register_operand" "=x,x") (if_then_else:VI_128 (ge:VI_128 @@ -11366,7 +11366,7 @@ (set_attr "prefix_extra" "2") (set_attr "mode" "TI")]) -(define_insn "xop_lshl3" +(define_insn "xop_shl3" [(set (match_operand:VI_128 0 "register_operand" "=x,x") (if_then_else:VI_128 (ge:VI_128 @@ -11402,7 +11402,7 @@ XVECEXP (par, 0, i) = operands[2]; emit_insn (gen_vec_initv16qi (reg, par)); - emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg)); + emit_insn (gen_xop_shav16qi3 (operands[0], operands[1], reg)); DONE; }) @@ -11434,9 +11434,9 @@ emit_insn (gen_negv16qi2 (reg, reg)); if ( == LSHIFTRT) - shift_insn = gen_xop_lshlv16qi3; + shift_insn = gen_xop_shlv16qi3; else - shift_insn = gen_xop_ashlv16qi3; + shift_insn = gen_xop_shav16qi3; emit_insn (shift_insn (operands[0], operands[1], reg)); DONE; @@ -11468,7 +11468,7 @@ if (negate) emit_insn (gen_negv2di2 (reg, reg)); - emit_insn (gen_xop_ashlv2di3 (operands[0], operands[1], reg)); + emit_insn (gen_xop_shav2di3 (operands[0], operands[1], reg)); DONE; })