From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Thu, 25 Feb 2010 22:10:38 +0000 (+0000)
Subject: Merge branches 'clks' and 'pnx' into devel
X-Git-Tag: v3.12-rc1~11254^2
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9f33be2c3a80bdc2cc08342dd77fac87652e0548;p=kernel%2Fkernel-generic.git

Merge branches 'clks' and 'pnx' into devel
---

9f33be2c3a80bdc2cc08342dd77fac87652e0548
diff --cc arch/arm/mach-ep93xx/clock.c
index 49fa9f8,bb3c621..5f80092
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@@ -447,16 -445,13 +447,15 @@@ static void __init ep93xx_dma_clock_ini
  static int __init ep93xx_clock_init(void)
  {
  	u32 value;
- 	int i;
  
 -	value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
 -	if (!(value & 0x00800000)) {			/* PLL1 bypassed?  */
 +	/* Determine the bootloader configured pll1 rate */
 +	value = __raw_readl(EP93XX_SYSCON_CLKSET1);
 +	if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
  		clk_pll1.rate = clk_xtali.rate;
 -	} else {
 +	else
  		clk_pll1.rate = calc_pll_rate(value);
 -	}
 +
 +	/* Initialize the pll1 derived clocks */
  	clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
  	clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
  	clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];