From: Marek Olšák Date: Thu, 23 Sep 2021 11:17:58 +0000 (-0400) Subject: radeonsi: remove the unused cs parameter from radeon_emit_array X-Git-Tag: upstream/22.3.5~17510 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9f0cd15d6a7a1ad25b9f360afb2e9026020dcf3c;p=platform%2Fupstream%2Fmesa.git radeonsi: remove the unused cs parameter from radeon_emit_array Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h index 1e66d7e..80aae14 100644 --- a/src/gallium/drivers/radeonsi/si_build_pm4.h +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h @@ -67,7 +67,7 @@ (sctx)->context_roll = true; \ } while (0) -#define radeon_emit_array(cs, values, num) do { \ +#define radeon_emit_array(values, num) do { \ unsigned __n = (num); \ memcpy(__cs_buf + __cs_num, (values), __n * 4); \ __cs_num += __n; \ @@ -99,7 +99,7 @@ #define radeon_set_context_reg_seq_array(cs, reg, num, values) do { \ radeon_set_context_reg_seq(cs, reg, num); \ - radeon_emit_array(cs, values, num); \ + radeon_emit_array(values, num); \ } while (0) #define radeon_set_context_reg_idx(cs, reg, idx, value) do { \ @@ -254,7 +254,7 @@ #define radeon_opt_set_context_regn(sctx, offset, value, saved_val, num) do { \ if (memcmp(value, saved_val, sizeof(uint32_t) * (num))) { \ radeon_set_context_reg_seq(&(sctx)->gfx_cs, offset, num); \ - radeon_emit_array(cs, value, num); \ + radeon_emit_array(value, num); \ memcpy(saved_val, value, sizeof(uint32_t) * (num)); \ } \ } while (0) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index b3eaa0d..16e41d9 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -757,7 +757,7 @@ static void si_setup_nir_user_data(struct si_context *sctx, const struct pipe_gr if (sel->info.base.cs.user_data_components_amd) { radeon_set_sh_reg_seq(cs, cs_user_data_reg, sel->info.base.cs.user_data_components_amd); - radeon_emit_array(cs, sctx->cs_user_data, sel->info.base.cs.user_data_components_amd); + radeon_emit_array(sctx->cs_user_data, sel->info.base.cs.user_data_components_amd); } radeon_end(); } diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c index c25b304..ca22306 100644 --- a/src/gallium/drivers/radeonsi/si_cp_dma.c +++ b/src/gallium/drivers/radeonsi/si_cp_dma.c @@ -495,7 +495,7 @@ void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned radeon_emit(S_370_DST_SEL(dst_sel) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine)); radeon_emit(va); radeon_emit(va >> 32); - radeon_emit_array(cs, (const uint32_t *)data, size / 4); + radeon_emit_array((const uint32_t *)data, size / 4); radeon_end(); } diff --git a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c index 572905b..5fff90f 100644 --- a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c +++ b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c @@ -143,7 +143,7 @@ static void si_set_context_reg_array(struct radeon_cmdbuf *cs, unsigned reg, uns { radeon_begin(cs); radeon_set_context_reg_seq(cs, reg, num); - radeon_emit_array(cs, values, num); + radeon_emit_array(values, num); radeon_end(); } diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 0a563b3..217afe4 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -2166,7 +2166,7 @@ void si_emit_compute_shader_pointers(struct si_context *sctx) num_shaderbufs * 4); for (unsigned i = 0; i < num_shaderbufs; i++) - radeon_emit_array(cs, &desc->list[si_get_shaderbuf_slot(i) * 4], 4); + radeon_emit_array(&desc->list[si_get_shaderbuf_slot(i) * 4], 4); sctx->compute_shaderbuf_sgprs_dirty = false; } @@ -2190,7 +2190,7 @@ void si_emit_compute_shader_pointers(struct si_context *sctx) num_sgprs = 4; } - radeon_emit_array(cs, &desc->list[desc_offset], num_sgprs); + radeon_emit_array(&desc->list[desc_offset], num_sgprs); } sctx->compute_image_sgprs_dirty = false; diff --git a/src/gallium/drivers/radeonsi/si_pm4.c b/src/gallium/drivers/radeonsi/si_pm4.c index 8213fe3..ae4affa 100644 --- a/src/gallium/drivers/radeonsi/si_pm4.c +++ b/src/gallium/drivers/radeonsi/si_pm4.c @@ -123,7 +123,7 @@ void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state) } radeon_begin(cs); - radeon_emit_array(cs, state->pm4, state->ndw); + radeon_emit_array(state->pm4, state->ndw); radeon_end(); if (state->atom.emit) diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c index 63d5bbc..b712df9 100644 --- a/src/gallium/drivers/radeonsi/si_sqtt.c +++ b/src/gallium/drivers/radeonsi/si_sqtt.c @@ -737,7 +737,7 @@ si_emit_thread_trace_userdata(struct si_context* sctx, * write on correctly. */ radeon_set_uconfig_reg_seq(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count, sctx->chip_class >= GFX10); - radeon_emit_array(cs, dwords, count); + radeon_emit_array(dwords, count); dwords += count; num_dwords -= count; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 6438eb3..4dd331a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -764,7 +764,7 @@ static void si_emit_blend_color(struct si_context *sctx) radeon_begin(cs); radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4); - radeon_emit_array(cs, (uint32_t *)sctx->blend_color.color, 4); + radeon_emit_array((uint32_t *)sctx->blend_color.color, 4); radeon_end(); } @@ -798,7 +798,7 @@ static void si_emit_clip_state(struct si_context *sctx) radeon_begin(cs); radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6 * 4); - radeon_emit_array(cs, (uint32_t *)sctx->clip_state.ucp, 6 * 4); + radeon_emit_array((uint32_t *)sctx->clip_state.ucp, 6 * 4); radeon_end(); } diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 2bc349a..a711952 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -1461,7 +1461,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */ radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, sctx->num_vs_blit_sgprs); - radeon_emit_array(cs, sctx->vs_blit_sh_data, sctx->num_vs_blit_sgprs); + radeon_emit_array(sctx->vs_blit_sh_data, sctx->num_vs_blit_sgprs); } else if (base_vertex != sctx->last_base_vertex || sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN || (set_base_instance && @@ -1796,7 +1796,7 @@ static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx) unsigned num_sgprs = MIN2(count, num_vbos_in_user_sgprs) * 4; radeon_set_sh_reg_seq(cs, sh_base + SI_SGPR_VS_VB_DESCRIPTOR_FIRST * 4, num_sgprs); - radeon_emit_array(cs, sctx->vb_descriptor_user_sgprs, num_sgprs); + radeon_emit_array(sctx->vb_descriptor_user_sgprs, num_sgprs); sctx->vertex_buffer_user_sgprs_dirty = false; } radeon_end(); diff --git a/src/gallium/drivers/radeonsi/si_state_msaa.c b/src/gallium/drivers/radeonsi/si_state_msaa.c index 32f4e75..b33cbe5 100644 --- a/src/gallium/drivers/radeonsi/si_state_msaa.c +++ b/src/gallium/drivers/radeonsi/si_state_msaa.c @@ -170,10 +170,10 @@ static void si_emit_max_16_sample_locs(struct radeon_cmdbuf *cs, uint64_t centro radeon_emit(centroid_priority >> 32); radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, num_samples == 8 ? 14 : 16); - radeon_emit_array(cs, sample_locs, 4); - radeon_emit_array(cs, sample_locs, 4); - radeon_emit_array(cs, sample_locs, 4); - radeon_emit_array(cs, sample_locs, num_samples == 8 ? 2 : 4); + radeon_emit_array(sample_locs, 4); + radeon_emit_array(sample_locs, 4); + radeon_emit_array(sample_locs, 4); + radeon_emit_array(sample_locs, num_samples == 8 ? 2 : 4); radeon_end(); }