From: Sujith Manoharan Date: Wed, 11 Sep 2013 06:10:58 +0000 (+0530) Subject: ath9k: Fix issue with parsing malformed CFP IE X-Git-Tag: v3.13-rc1~105^2~225^2~40 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9ef48932344a8ea9d6d1628d92afc2c5d6958336;p=profile%2Fcommon%2Fkernel-common.git ath9k: Fix issue with parsing malformed CFP IE All QCA chips have the ability to parse the CF Parameter Set IE in beacons. If the IE is malformed in the beacons from some APs [1], the HW locks up. In AP mode, a beacon stuck would happen and in client mode, a disconnection usually is the result. To fix this issue, set the AR_PCU_MISC_MODE2_CFP_IGNORE to ignore the CFP IE in beacons - this is applicable for all chips. For AP mode, if this issue happens, the NAV is also corrupted and has to be reset - this will be done in a subsequent patch. [1] : http://msujith.org/ath9k/cfp/Malformed-CF-Param.png Signed-off-by: Sujith Manoharan Signed-off-by: John W. Linville --- diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c index 0865647..9e4e2a6 100644 --- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c @@ -626,6 +626,8 @@ static void ar5008_hw_override_ini(struct ath_hw *ah, if (AR_SREV_9287_11_OR_LATER(ah)) val = val & (~AR_PCU_MISC_MODE2_HWWAR2); + val |= AR_PCU_MISC_MODE2_CFP_IGNORE; + REG_WRITE(ah, AR_PCU_MISC_MODE2, val); } diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index b8a279e..ec37213 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c @@ -627,8 +627,10 @@ static void ar9003_hw_override_ini(struct ath_hw *ah) * MAC addr only will fail. */ val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); - REG_WRITE(ah, AR_PCU_MISC_MODE2, - val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); + val |= AR_AGG_WEP_ENABLE_FIX | + AR_AGG_WEP_ENABLE | + AR_PCU_MISC_MODE2_CFP_IGNORE; + REG_WRITE(ah, AR_PCU_MISC_MODE2, val); REG_SET_BIT(ah, AR_PHY_CCK_DETECT, AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);