From: Richard Henderson <rth@twiddle.net>
Date: Fri, 11 Dec 2009 17:07:29 +0000 (-0800)
Subject: target-alpha: Fix fbcond branch offset.
X-Git-Tag: TizenStudio_2.0_p2.3~6252
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9ef1b002d049c2d04f8f1292c3bebc97c5102990;p=sdk%2Femulator%2Fqemu.git

target-alpha: Fix fbcond branch offset.

The instructions use a disp21 like all other branch insns,
not the disp16 that was being passed.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---

diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 029bcd9..fbcedde 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -314,8 +314,7 @@ static inline void gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
     gen_set_label(l2);
 }
 
-static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
-                              int32_t disp16)
+static inline void gen_fbcond(DisasContext *ctx, int opc, int ra, int32_t disp)
 {
     int l1, l2;
     TCGv tmp;
@@ -356,7 +355,7 @@ static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
     tcg_gen_movi_i64(cpu_pc, ctx->pc);
     tcg_gen_br(l2);
     gen_set_label(l1);
-    tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
+    tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
     gen_set_label(l2);
 }
 
@@ -2335,7 +2334,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
     case 0x31: /* FBEQ */
     case 0x32: /* FBLT */
     case 0x33: /* FBLE */
-        gen_fbcond(ctx, opc, ra, disp16);
+        gen_fbcond(ctx, opc, ra, disp21);
         ret = 1;
         break;
     case 0x34:
@@ -2348,7 +2347,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
     case 0x35: /* FBNE */
     case 0x36: /* FBGE */
     case 0x37: /* FBGT */
-        gen_fbcond(ctx, opc, ra, disp16);
+        gen_fbcond(ctx, opc, ra, disp21);
         ret = 1;
         break;
     case 0x38: