From: Andrew Cagney <cagney@redhat.com>
Date: Sat, 31 Jan 1998 06:23:41 +0000 (+0000)
Subject: igen:	Fix SMP simulator generator support.
X-Git-Tag: gdb-4_18~3565
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9ec6741b177fbd4d872a13002d540b60b11e4b78;p=external%2Fbinutils.git

igen:	Fix SMP simulator generator support.
	Use the bfd-processor name in the sim-engine switch.
	Add nr_cpus argument to sim_engine_run.
tic80, v850, d30v, mips, common:
	Update
mips:	Fill in bfd-processor field of model records so that
	they match ../bfd/archures.
---

diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog
index 028127a..11cf423 100644
--- a/sim/common/ChangeLog
+++ b/sim/common/ChangeLog
@@ -1,3 +1,21 @@
+Fri Jan 30 09:36:33 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* sim-engine.h (sim_engine_run): Add argument nr_cpus.
+	* sim-run.c (sim_engine_run): Update.
+	
+	* sim-engine.h (SIM_ENGINE_HALT_HOOK): Use SET_CPU_CIA instead of
+ 	CPU_CIA.
+  	* sim-run.c (sim_engine_run): Ditto.
+
+	* sim-resume.c (sim_resume): Obtain nr_cpus from sim_engine.
+	(sim_resume): Pass nr_cpus to sim_engine_run.
+
+	* sim-engine.h (struct _sim_engine): Add member nr_cpus.
+	
+	* sim-engine.c (sim_engine_init): Hardwire nr_cpus to
+ 	MAX_NR_PROCESSORS.
+	(sim_engine_nr_cpus) sim-engine.c, sim-engine.h: New function
+	
 Thu Jan 29 12:13:01 1998  Doug Evans  <devans@canuck.cygnus.com>
 
 	* cgen.sh: Portably read parms past $9.
diff --git a/sim/igen/ChangeLog b/sim/igen/ChangeLog
index 36f82c1..7db04df 100644
--- a/sim/igen/ChangeLog
+++ b/sim/igen/ChangeLog
@@ -1,3 +1,30 @@
+Sat Jan 31 14:50:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* gen-engine.c (print_run_body): Use CIA_GET & CIA_SET instead of
+ 	CPU_CIA.  Parameterize with CPU argument.
+
+Fri Jan 30 09:09:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* gen.h (struct _gen_list): Replace processor with model.
+
+	* igen.c (gen_idecode_h): Update.
+	(gen_run_c): For generated switch, use model->full_name.
+
+	* gen.c (print_gen_entry_path): Ditto.
+	(make_table):  Ditto.
+	(gen_entry_expand_insns):  Ditto.
+	(make_gen_tables):  Ditto.
+
+	* igen.c (gen_run_c): Add extra argument `nr_cpus' to generated
+ 	function sim_engine_run.  Pass argument on to engine_run.
+
+	* gen-engine.c (print_engine_run_function_header): Add extra
+ 	argument `nr_cpus' to generated function engine_run.
+	(print_run_body): Fix SMP case.
+
+	* gen-support.c (support_c_function): Call sim_engine_abort when
+ 	internal function fails to long jump.
+
 Wed Jan 21 18:00:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* gen-semantics.c (print_semantic_body): Use GPR_SET to zero
diff --git a/sim/igen/gen-engine.c b/sim/igen/gen-engine.c
new file mode 100644
index 0000000..5290e73
--- /dev/null
+++ b/sim/igen/gen-engine.c
@@ -0,0 +1,785 @@
+/*  This file is part of the program psim.
+
+    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+ 
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ 
+    */
+
+#include "misc.h"
+#include "lf.h"
+#include "table.h"
+#include "filter.h"
+
+#include "igen.h"
+
+#include "ld-insn.h"
+#include "ld-decode.h"
+
+#include "gen.h"
+
+#include "gen-idecode.h"
+#include "gen-engine.h"
+#include "gen-icache.h"
+#include "gen-semantics.h"
+
+
+static void
+print_run_body (lf *file,
+	        gen_entry *table)
+{
+  /* Output the function to execute real code:
+     
+     Unfortunatly, there are multiple cases to consider vis:
+     
+     <icache> X <smp>
+     
+     Consequently this function is written in multiple different ways */
+  
+  lf_printf (file, "{\n");
+  lf_indent (file, +2);
+  if (!options.gen.smp)
+    {
+      lf_printf (file, "instruction_address cia;\n");
+    }
+  lf_printf (file, "int current_cpu = next_cpu_nr;\n");
+  
+  if (options.gen.icache)
+    {
+      lf_printf (file, "/* flush the icache of a possible break insn */\n");
+      lf_printf (file, "{\n");
+      lf_printf (file, "  int cpu_nr;\n");
+      lf_printf (file, "  for (cpu_nr = 0; cpu_nr < nr_cpus; cpu_nr++)\n");
+      lf_printf (file, "    cpu_flush_icache (STATE_CPU (sd, cpu_nr));\n");
+      lf_printf (file, "}\n");
+    }
+  
+  if (!options.gen.smp)
+    {
+      
+      lf_putstr (file, "
+/* CASE 1: NO SMP (with or with out instruction cache).
+
+In this case, we can take advantage of the fact that the current
+instruction address (CIA) does not need to be read from / written to
+the CPU object after the execution of an instruction.
+
+Instead, CIA is only saved when the main loop exits.  This occures
+when either sim_engine_halt or sim_engine_restart is called.  Both of
+these functions save the current instruction address before halting /
+restarting the simulator.
+
+As a variation, there may also be support for an instruction cracking
+cache. */
+
+");
+
+      lf_putstr (file, "\n");
+      lf_putstr (file, "/* prime the main loop */\n");
+      lf_putstr (file, "SIM_ASSERT (current_cpu == 0);\n");
+      lf_putstr (file, "SIM_ASSERT (nr_cpus == 1);\n");
+      lf_putstr (file, "cia = CIA_GET (CPU);\n");
+
+      lf_putstr (file, "\n");
+      lf_putstr (file, "while (1)\n");
+      lf_putstr (file, "  {\n");
+      lf_indent (file, +4);
+      
+      lf_printf (file, "%sinstruction_address nia;\n",
+		 options.prefix.global.name);
+
+      lf_printf (file, "\n");
+      if (!options.gen.icache)
+	{
+	  lf_printf (file, "%sinstruction_word instruction_0 = IMEM (cia);\n",
+		     options.prefix.global.name);
+	  lf_printf (file, "\n");
+	  lf_indent_suppress (file);
+	  lf_printf (file, "#if defined (%sENGINE_ISSUE_PREFIX_HOOK)\n",
+		     options.prefix.global.name);
+	  lf_printf (file, "%sENGINE_ISSUE_PREFIX_HOOK();\n",
+		     options.prefix.global.name);
+	  lf_indent_suppress (file);
+	  lf_printf (file, "#endif\n");
+	  lf_printf (file, "\n");
+	  print_idecode_body (file, table, "nia = ");
+	  lf_printf (file, "\n");
+	  lf_indent_suppress (file);
+	  lf_printf (file, "#if defined (%sENGINE_ISSUE_POSTFIX_HOOK)\n",
+		     options.prefix.global.name);
+	  lf_printf (file, "%sENGINE_ISSUE_POSTFIX_HOOK();\n",
+		     options.prefix.global.name);
+	  lf_indent_suppress (file);
+	  lf_printf (file, "#endif\n");
+	  lf_printf (file, "\n");
+	}
+      else
+	{
+	  lf_putstr (file, "idecode_cache *cache_entry =\n");
+	  lf_putstr (file, "  cpu_icache_entry (cpu, cia);\n");
+	  lf_putstr (file, "if (cache_entry->address == cia)\n");
+	  lf_putstr (file, "  {\n");
+	  lf_indent (file, -4);
+	  lf_putstr (file, "/* cache hit */\n");
+	  lf_putstr (file, "idecode_semantic *const semantic = cache_entry->semantic;\n");
+	  lf_putstr (file, "cia = semantic (cpu, cache_entry, cia);\n");
+	  /* tail */
+	  lf_indent (file, -4);
+	  lf_putstr (file, "  }\n");
+	  lf_putstr (file, "else\n");
+	  lf_putstr (file, "  {\n");
+	  lf_indent (file, +4);
+	  lf_putstr (file, "/* cache miss */\n");
+	  if (!options.gen.semantic_icache)
+	    {
+	      lf_putstr (file, "idecode_semantic *semantic;\n");
+	    }
+	  lf_putstr (file, "instruction_word instruction = IMEM (cia);\n");
+	  lf_putstr (file, "if (WITH_MON != 0)\n");
+	  lf_putstr (file, "  mon_event (mon_event_icache_miss, cpu, cia);\n");
+	  if (options.gen.semantic_icache)
+	    {
+	      lf_putstr (file, "{\n");
+	      lf_indent (file, +2);
+	      print_idecode_body (file, table, "nia =");
+	      lf_indent (file, -2);
+	      lf_putstr (file, "}\n");
+	    }
+	  else
+	    {
+	      print_idecode_body (file, table, "semantic =");
+	      lf_putstr (file, "nia = semantic (cpu, cache_entry, cia);\n");
+	    }
+	  lf_indent (file, -4);
+	  lf_putstr (file, "  }\n");
+	}
+      
+      /* update the cpu if necessary */
+      switch (options.gen.nia)
+	{
+	case nia_is_cia_plus_one:
+	  lf_printf (file, "\n");
+	  lf_printf (file, "/* Update the instruction address */\n");
+	  lf_printf (file, "cia = nia;\n");
+	  break;
+	case nia_is_void:
+	case nia_is_invalid:
+	  ERROR ("engine gen when NIA complex");
+	}
+
+      /* events */
+      lf_putstr (file, "\n");
+      lf_putstr (file, "/* process any events */\n");
+      lf_putstr (file, "if (sim_events_tick (sd))\n");
+      lf_putstr (file, "  {\n");
+      lf_putstr (file, "    CIA_SET (CPU, cia);\n");
+      lf_putstr (file, "    sim_events_process (sd);\n");
+      lf_putstr (file, "  }\n");
+
+      lf_indent (file, -4);
+      lf_printf (file, "  }\n");
+    }
+  
+  if (options.gen.smp)
+    {
+      
+      lf_putstr (file, "
+/* CASE 2: SMP (With or without ICACHE)
+
+The complexity here comes from needing to correctly halt the simulator
+when it is aborted.  For instance, if cpu0 requests a restart then
+cpu1 will normally be the next cpu that is run.  Cpu0 being restarted
+after all the other CPU's and the event queue have been processed */
+
+");
+      
+      lf_putstr (file, "\n");
+      lf_printf (file, "/* have ensured that the event queue is current */\n");
+      lf_printf (file, "SIM_ASSERT (current_cpu >= 0);\n");
+      lf_printf (file, "SIM_ASSERT (current_cpu < nr_cpus - 1);\n");
+      lf_printf (file, "SIM_ASSERT (nr_cpus <= MAX_NR_PROCESSORS);\n");
+
+      lf_putstr (file, "\n");
+      lf_putstr (file, "while (1)\n");
+      lf_putstr (file, "  {\n");
+      lf_indent (file, +4);
+      
+      lf_putstr (file, "\n");
+      lf_putstr (file, "current_cpu += 1;\n");
+      lf_putstr (file, "if (current_cpu == nr_cpus)\n");
+      lf_putstr (file, "  {\n");
+      lf_putstr (file, "    if (sim_events_tick (sd))\n");
+      lf_putstr (file, "      {\n");
+      lf_putstr (file, "        sim_events_process (sd);\n");
+      lf_putstr (file, "      }\n");
+      lf_putstr (file, "    current_cpu = 0;\n");
+      lf_putstr (file, "  }\n");
+      
+      lf_putstr (file, "\n");
+      lf_putstr (file, "{\n");
+      lf_indent (file, +2);
+      lf_putstr (file, "sim_cpu *cpu = STATE_CPU (sd, current_cpu);\n");
+      lf_putstr (file, "instruction_address cia = CIA_GET (cpu);\n");
+      
+      if (!options.gen.icache)
+	{
+	  lf_putstr (file, "instruction_word instruction_0 = IMEM (cia);\n");
+	  print_idecode_body (file, table, "cia =");
+	  lf_putstr (file, "CIA_SET (cpu, cia);\n");
+	}
+      
+      if (options.gen.icache)
+	{
+	  lf_putstr (file, "engine_cache *cache_entry =\n");
+	  lf_putstr (file, "  cpu_icache_entry(processor, cia);\n");
+	  lf_putstr (file, "\n");
+	  lf_putstr (file, "if (cache_entry->address == cia) {\n");
+	  {
+	    lf_indent (file, +2);
+	    lf_putstr (file, "\n");
+	    lf_putstr (file, "/* cache hit */\n");
+	    lf_putstr (file, "engine_semantic *semantic = cache_entry->semantic;\n");
+	    lf_putstr (file, "cia = semantic(processor, cache_entry, cia);\n");
+	    /* tail */
+	    lf_putstr (file, "cpu_set_program_counter(processor, cia);\n");
+	    lf_putstr (file, "\n");
+	    lf_indent (file, -2);
+	  }
+	  lf_putstr (file, "}\n");
+	  lf_putstr (file, "else {\n");
+	  {
+	    lf_indent (file, +2);
+	    lf_putstr (file, "\n");
+	    lf_putstr (file, "/* cache miss */\n");
+	    if (!options.gen.semantic_icache)
+	      {
+		lf_putstr (file, "engine_semantic *semantic;\n");
+	      }
+	    lf_putstr (file, "instruction_word instruction = IMEM (cia);\n");
+	    lf_putstr (file, "if (WITH_MON != 0)\n");
+	    lf_putstr (file, "  mon_event(mon_event_icache_miss, processors[current_cpu], cia);\n");
+	    if (options.gen.semantic_icache)
+	      {
+		lf_putstr (file, "{\n");
+		lf_indent (file, +2);
+		print_idecode_body(file, table, "cia =");
+		lf_indent (file, -2);
+		lf_putstr (file, "}\n");
+	      }
+	    else
+	      {
+		print_idecode_body(file, table, "semantic = ");
+		lf_putstr (file, "cia = semantic(processor, cache_entry, cia);\n");
+	      }
+	    /* tail */
+	    lf_putstr (file, "cpu_set_program_counter(processor, cia);\n");
+	    lf_putstr (file, "\n");
+	    lf_indent (file, -2);
+	  }
+	  lf_putstr (file, "}\n");
+	}
+      
+      /* close */
+      lf_indent (file, -2);
+      lf_putstr (file, "}\n");
+      
+      /* tail */
+      lf_indent (file, -4);
+      lf_putstr (file, "  }\n");
+    }
+  
+  
+  lf_indent (file, -2);
+  lf_putstr (file, "}\n");
+}
+
+
+/****************************************************************/
+
+#if 0
+static void
+print_jump (lf *file,
+	    int is_tail)
+{
+  if (!options.gen.smp)
+    {
+      lf_putstr (file, "if (event_queue_tick (sd))\n");
+      lf_putstr (file, "  {\n");
+      lf_putstr (file, "    CPU_CIA (processor) = nia;\n");
+      lf_putstr (file, "    sim_events_process (sd);\n");
+      lf_putstr (file, "  }\n");
+      lf_putstr (file, "}\n");
+    }
+  
+  if (options.gen.smp)
+    {
+      if (is_tail)
+	lf_putstr (file, "cpu_set_program_counter(processor, nia);\n");
+      lf_putstr (file, "current_cpu += 1;\n");
+      lf_putstr (file, "if (current_cpu >= nr_cpus)\n");
+      lf_putstr (file, "  {\n");
+      lf_putstr (file, "    if (sim_events_tick (sd))\n");
+      lf_putstr (file, "      {\n");
+      lf_putstr (file, "        sim_events_process (sd);\n");
+      lf_putstr (file, "      }\n");
+      lf_putstr (file, "    current_cpu = 0;\n");
+      lf_putstr (file, "  }\n");
+      lf_putstr (file, "processor = processors[current_cpu];\n");
+      lf_putstr (file, "nia = cpu_get_program_counter(processor);\n");
+    }
+  
+  if (options.gen.icache)
+    {
+      lf_putstr (file, "cache_entry = cpu_icache_entry(processor, nia);\n");
+      lf_putstr (file, "if (cache_entry->address == nia) {\n");
+      lf_putstr (file, "  /* cache hit */\n");
+      lf_putstr (file, "  goto *cache_entry->semantic;\n");
+      lf_putstr (file, "}\n");
+      if (is_tail) {
+	lf_putstr (file, "goto cache_miss;\n");
+      }
+    }
+  
+  if (!options.gen.icache && is_tail)
+    {
+      lf_printf (file, "goto engine;\n");
+    }
+  
+}
+#endif
+
+
+#if 0
+static void
+print_jump_insn (lf *file,
+		 insn_entry *instruction,
+		 opcode_bits *expanded_bits,
+		 opcode_field *opcodes,
+		 cache_entry *cache_rules)
+{
+  insn_opcodes opcode_path;
+
+  memset (&opcode_path, 0, sizeof (opcode_path));
+  opcode_path.opcode = opcodes;
+
+  /* what we are for the moment */
+  lf_printf (file, "\n");
+  print_my_defines (file,
+		    instruction->name,
+		    instruction->format_name,
+		    expanded_bits);
+  
+  /* output the icache entry */
+  if (options.gen.icache)
+    {
+      lf_printf (file, "\n");
+      lf_indent (file, -1);
+      print_function_name (file,
+			   instruction->name,
+			   instruction->format_name,
+			   NULL,
+			   expanded_bits,
+			   function_name_prefix_icache);
+      lf_printf (file, ":\n");
+      lf_indent (file, +1);
+      lf_printf (file, "{\n");
+      lf_indent (file, +2);
+      lf_putstr (file, "const unsigned_word cia = nia;\n");
+      print_itrace (file, instruction, 1/*putting-value-in-cache*/);
+      print_idecode_validate (file, instruction, &opcode_path);
+      lf_printf (file, "\n");
+      lf_printf (file, "{\n");
+      lf_indent (file, +2);
+      print_icache_body (file,
+			 instruction,
+			 expanded_bits,
+			 cache_rules,
+			 0, /*use_defines*/
+			 put_values_in_icache);
+      lf_printf (file, "cache_entry->address = nia;\n");
+      lf_printf (file, "cache_entry->semantic = &&");
+      print_function_name (file,
+			   instruction->name,
+			   instruction->format_name,
+			   NULL,
+			   expanded_bits,
+			   function_name_prefix_semantics);
+      lf_printf (file, ";\n");
+      if (options.gen.semantic_icache)
+	{
+	  print_semantic_body (file,
+			       instruction,
+			       expanded_bits,
+			       &opcode_path);
+	  print_jump(file, 1/*is-tail*/);
+	}
+      else
+	{
+	  lf_printf (file, "/* goto ");
+	  print_function_name (file,
+			       instruction->name,
+			       instruction->format_name,
+			       NULL,
+			       expanded_bits,
+			       function_name_prefix_semantics);
+	  lf_printf (file, "; */\n");
+	}
+      lf_indent (file, -2);
+      lf_putstr (file, "}\n");
+      lf_indent (file, -2);
+      lf_printf (file, "}\n");
+    }
+  
+  /* print the semantics */
+  lf_printf (file, "\n");
+  lf_indent (file, -1);
+  print_function_name (file,
+		       instruction->name,
+		       instruction->format_name,
+		       NULL,
+		       expanded_bits,
+		       function_name_prefix_semantics);
+  lf_printf (file, ":\n");
+  lf_indent (file, +1);
+  lf_printf (file, "{\n");
+  lf_indent (file, +2);
+  lf_putstr (file, "const unsigned_word cia = nia;\n");
+  print_icache_body (file,
+		     instruction,
+		     expanded_bits,
+		     cache_rules,
+		     (options.gen.direct_access
+		      ? define_variables
+		      : declare_variables),
+		     (options.gen.icache
+		      ? get_values_from_icache
+		      : do_not_use_icache));
+  print_semantic_body (file,
+		       instruction,
+		       expanded_bits,
+		       &opcode_path);
+  if (options.gen.direct_access)
+    print_icache_body (file,
+		       instruction,
+		       expanded_bits,
+		       cache_rules,
+		       undef_variables,
+		       (options.gen.icache
+			? get_values_from_icache
+			: do_not_use_icache));
+  print_jump(file, 1/*is tail*/);
+  lf_indent (file, -2);
+  lf_printf (file, "}\n");
+}
+#endif
+
+
+#if 0
+static void
+print_jump_definition (lf *file,
+		       gen_entry *entry,
+		       int depth,
+		       void *data)
+{
+  cache_entry *cache_rules = (cache_entry*)data;
+  if (entry->opcode_rule->with_duplicates)
+    {
+      ASSERT (entry->nr_insns == 1
+	      && entry->opcode == NULL
+	      && entry->parent != NULL
+	      && entry->parent->opcode != NULL);
+      ASSERT (entry->nr_insns == 1
+	      && entry->opcode == NULL
+	      && entry->parent != NULL
+	      && entry->parent->opcode != NULL
+	      && entry->parent->opcode_rule != NULL);
+      print_jump_insn (file,
+		       entry->insns->insn,
+		       entry->expanded_bits,
+		       entry->opcode,
+		       cache_rules);
+    }
+  else 
+    {
+      print_jump_insn (file,
+		       entry->insns->insn,
+		       NULL,
+		       NULL,
+		       cache_rules);
+    }
+}
+#endif
+
+
+#if 0
+static void
+print_jump_internal_function (lf *file,
+			      function_entry *function,
+			      void *data)
+{
+  if (function->is_internal)
+    {
+      lf_printf (file, "\n");
+      lf_print__line_ref (file, function->line);
+      lf_indent (file, -1);
+      print_function_name (file,
+			   function->name,
+			   NULL,
+			   NULL,
+			   NULL,
+			   (options.gen.icache
+			    ? function_name_prefix_icache
+			    : function_name_prefix_semantics));
+      lf_printf (file, ":\n");
+      lf_indent (file, +1);
+      lf_printf (file, "{\n");
+      lf_indent (file, +2);
+      lf_printf (file, "const unsigned_word cia = nia;\n");
+      table_print_code (file, function->code);
+      lf_print__internal_ref (file);
+      lf_printf (file, "error(\"Internal function must longjump\\n\");\n");
+      lf_indent (file, -2);
+      lf_printf (file, "}\n");
+    }
+}
+#endif
+
+
+#if 0
+static void
+print_jump_body (lf *file,
+		 gen_entry *entry,
+		 insn_table *isa,
+		 cache_entry *cache_rules)
+{
+  lf_printf (file, "{\n");
+  lf_indent (file, +2);
+  lf_putstr (file, "jmp_buf halt;\n");
+  lf_putstr (file, "jmp_buf restart;\n");
+  lf_putstr (file, "cpu *processor = NULL;\n");
+  lf_putstr (file, "unsigned_word nia = -1;\n");
+  lf_putstr (file, "instruction_word instruction = 0;\n");
+  if (options.gen.icache)
+    {
+      lf_putstr (file, "engine_cache *cache_entry = NULL;\n");
+    }
+  if (options.gen.smp)
+    {
+      lf_putstr (file, "int current_cpu = -1;\n");
+    }
+  
+  /* all the switches and tables - they know about jumping */
+  print_idecode_lookups (file, entry, cache_rules);
+  
+  /* start the simulation up */
+  if (options.gen.icache)
+    {
+      lf_putstr (file, "\n");
+      lf_putstr (file, "{\n");
+      lf_putstr (file, "  int cpu_nr;\n");
+      lf_putstr (file, "  for (cpu_nr = 0; cpu_nr < nr_cpus; cpu_nr++)\n");
+      lf_putstr (file, "    cpu_flush_icache(processors[cpu_nr]);\n");
+      lf_putstr (file, "}\n");
+    }
+  
+  lf_putstr (file, "\n");
+  lf_putstr (file, "psim_set_halt_and_restart(system, &halt, &restart);\n");
+  
+  lf_putstr (file, "\n");
+  lf_putstr (file, "if (setjmp(halt))\n");
+  lf_putstr (file, "  return;\n");
+  
+  lf_putstr (file, "\n");
+  lf_putstr (file, "setjmp(restart);\n");
+  
+  lf_putstr (file, "\n");
+  if (!options.gen.smp)
+    {
+      lf_putstr (file, "processor = processors[0];\n");
+      lf_putstr (file, "nia = cpu_get_program_counter(processor);\n");
+    }
+  else
+    {
+      lf_putstr (file, "current_cpu = psim_last_cpu(system);\n");
+    }
+  
+  if (!options.gen.icache)
+    {
+      lf_printf (file, "\n");
+      lf_indent (file, -1);
+      lf_printf (file, "engine:\n");
+      lf_indent (file, +1);
+    }
+  
+  print_jump(file, 0/*is_tail*/);
+  
+  if (options.gen.icache)
+    {
+      lf_indent (file, -1);
+      lf_printf (file, "cache_miss:\n");
+      lf_indent (file, +1);
+    }
+  
+  lf_putstr (file, "instruction\n");
+  lf_putstr (file, "  = vm_instruction_map_read(cpu_instruction_map(processor),\n");
+  lf_putstr (file, "                            processor, nia);\n");
+  print_idecode_body (file, entry, "/*IGORE*/");
+  
+  /* print out a table of all the internals functions */
+  function_entry_traverse (file, isa->functions,
+			   print_jump_internal_function,
+			   NULL);
+  
+  /* print out a table of all the instructions */
+  ERROR ("Use the list of semantic functions, not travere_tree");
+  gen_entry_traverse_tree (file, entry,
+			   1,
+			   NULL, /* start */
+			   print_jump_definition, /* leaf */
+			   NULL, /* end */
+			   cache_rules);
+  lf_indent (file, -2);
+  lf_printf (file, "}\n");
+}
+#endif
+
+
+/****************************************************************/
+
+
+void
+print_engine_run_function_header (lf *file,
+				  char *processor,
+				  function_decl_type decl_type)
+{
+  int indent;
+  lf_printf (file, "\n");
+  switch (decl_type)
+    {
+    case is_function_declaration:
+      lf_print__function_type (file, "void", "INLINE_ENGINE", "\n");
+      break;
+    case is_function_definition:
+      lf_print__function_type (file, "void", "INLINE_ENGINE", " ");
+      break;
+    case is_function_variable:
+      lf_printf (file, "void (*");
+      break;
+    }
+  indent = print_function_name (file,
+				"run",
+				NULL, /* format name */
+				processor,
+				NULL, /* expanded bits */
+				function_name_prefix_engine);
+  switch (decl_type)
+    {
+    case is_function_definition:
+      lf_putstr (file, "\n(");
+      indent = 1;
+      break;
+    case is_function_declaration:
+      indent += lf_printf (file, " (");
+      break;
+    case is_function_variable:
+      lf_putstr (file, ")\n(");
+      indent = 1;
+      break;
+    }
+  lf_indent (file, +indent);
+  lf_printf (file, "SIM_DESC sd,\n");
+  lf_printf (file, "int next_cpu_nr,\n");
+  lf_printf (file, "int nr_cpus,\n");
+  lf_printf (file, "int siggnal)");
+  lf_indent (file, -indent);
+  switch (decl_type)
+    {
+    case is_function_definition:
+      lf_putstr (file, "\n");
+      break;
+    case is_function_variable:
+    case is_function_declaration:
+      lf_putstr (file, ";\n");
+      break;
+    }
+}
+
+
+void
+gen_engine_h (lf *file,
+	      gen_table *gen,
+	      insn_table *isa,
+	      cache_entry *cache_rules)
+{
+  gen_list *entry;
+  for (entry = gen->tables; entry != NULL; entry = entry->next)
+    {
+      print_engine_run_function_header (file,
+					entry->model->name,
+					is_function_declaration);
+    }
+}
+
+
+void
+gen_engine_c(lf *file,
+	     gen_table *gen,
+	     insn_table *isa,
+	     cache_entry *cache_rules)
+{
+  gen_list *entry;
+  /* the intro */
+  lf_printf (file, "#include \"sim-inline.c\"\n");
+  lf_printf (file, "\n");
+  lf_printf (file, "#include \"sim-main.h\"\n");
+  lf_printf (file, "#include \"itable.h\"\n");
+  lf_printf (file, "#include \"idecode.h\"\n");
+  lf_printf (file, "#include \"semantics.h\"\n");
+  lf_printf (file, "#include \"icache.h\"\n");
+  lf_printf (file, "#include \"engine.h\"\n");
+  lf_printf (file, "#include \"support.h\"\n");
+  lf_printf (file, "\n");
+  lf_printf (file, "#include \"sim-assert.h\"\n");
+  lf_printf (file, "\n");
+  print_idecode_globals (file);
+  lf_printf (file, "\n");
+
+  for (entry = gen->tables; entry != NULL; entry = entry->next)
+    {
+      switch (options.gen.code)
+	{
+	case generate_calls:
+	  print_idecode_lookups (file, entry->table, cache_rules);
+	  
+	  /* output the main engine routine */
+	  print_engine_run_function_header (file,
+					    entry->model->name,
+					    is_function_definition);
+	  print_run_body (file, entry->table);
+	  break;
+	  
+	case generate_jumps:
+	  ERROR ("Jumps currently unimplemented");
+#if 0
+	  print_engine_run_function_header (file,
+					    entry->processor,
+					    is_function_definition);
+	  print_jump_body (file, entry->table,
+			   isa, cache_rules);
+#endif
+	  break;
+	}
+    }
+}
diff --git a/sim/igen/gen-support.c b/sim/igen/gen-support.c
index bd8f34b..77f8eb4 100644
--- a/sim/igen/gen-support.c
+++ b/sim/igen/gen-support.c
@@ -110,19 +110,31 @@ extern void
 gen_support_h (lf *file,
 	       insn_table *table)
 {
-  /* output the definition of `_SD'*/
+  /* output the definition of `SD_'*/
   if (options.gen.smp) 
     {
-      lf_printf(file, "#define _SD cpu, cia, MY_INDEX\n");
+      lf_printf(file, "#define _SD cpu, cia, MY_INDEX /* depreciated */\n");
+      lf_printf(file, "#define SD_ cpu, cia, MY_INDEX\n");
       lf_printf(file, "#define SD CPU_STATE (cpu)\n");
       lf_printf(file, "#define CPU cpu\n");
     }
   else
     {
-      lf_printf(file, "#define _SD sd, cia, MY_INDEX\n");
+      lf_printf(file, "#define _SD sd, cia, MY_INDEX /* depreciated */\n");
+      lf_printf(file, "#define SD_ sd, cia, MY_INDEX\n");
       lf_printf(file, "#define SD sd\n");
       lf_printf(file, "#define CPU (STATE_CPU (sd, 0))\n");
     }
+  if (options.gen.delayed_branch)
+    {
+      lf_printf(file, "#define CIA cia.ip\n");
+      lf_printf(file, "/* #define NIA nia.dp -- do not define, ambigious */\n");
+    }
+  else
+    {
+      lf_printf(file, "#define CIA cia\n");
+      lf_printf(file, "#define NIA nia\n");
+    }
   lf_printf(file, "\n");
   /* output a declaration for all functions */
   function_entry_traverse (file, table->functions,
@@ -155,7 +167,7 @@ support_c_function (lf *file,
   table_print_code (file, function->code);
   if (function->is_internal)
     {
-      lf_printf (file, "sim_io_error (sd, \"Internal function must longjump\\n\");\n");
+      lf_printf (file, "sim_engine_abort (SD, CPU, cia, \"Internal function must longjump\\n\");\n");
       lf_printf (file, "return cia;\n");
     }
   lf_indent (file, -2);
diff --git a/sim/igen/igen.c b/sim/igen/igen.c
index afd2904..c1df4b3 100644
--- a/sim/igen/igen.c
+++ b/sim/igen/igen.c
@@ -353,7 +353,7 @@ static void
 print_itrace_format (lf *file,
 		     insn_mnemonic_entry *assembler)
 {
-  /* pass=1 is fmt string; pass=2 is is arguments */
+  /* pass=1 is fmt string; pass=2 is arguments */
   int pass;
   /* print the format string */
   for (pass = 1; pass <= 2; pass++)
@@ -786,9 +786,22 @@ gen_idecode_h (lf *file,
       gen_list *entry;
       for (entry = gen->tables; entry != NULL; entry = entry->next)
 	{
+	  if (entry->model != NULL)
+	    print_idecode_issue_function_header (file,
+						 entry->model->name,
+						 is_function_declaration,
+						 1/*ALWAYS ONE WORD*/);
+	  else
+	    print_idecode_issue_function_header (file,
+						 NULL,
+						 is_function_declaration,
+						 1/*ALWAYS ONE WORD*/);
+	}
+      if (options.gen.multi_sim)
+	{
 	  print_idecode_issue_function_header (file,
-					       entry->processor,
-					       0/*is definition*/,
+					       NULL,
+					       is_function_variable,
 					       1/*ALWAYS ONE WORD*/);
 	}
     }
@@ -825,10 +838,16 @@ gen_idecode_c (lf *file,
 	    /* output the main idecode routine */
 	    if (!options.gen.icache)
 	      {
-		print_idecode_issue_function_header (file,
-						     entry->processor,
-						     1/*is definition*/,
-						     1/*ALWAYS ONE WORD*/);
+		if (entry->model != NULL)
+		  print_idecode_issue_function_header (file,
+						       entry->model->name,
+						       1/*is definition*/,
+						       1/*ALWAYS ONE WORD*/);
+		else
+		  print_idecode_issue_function_header (file,
+						       NULL,
+						       1/*is definition*/,
+						       1/*ALWAYS ONE WORD*/);
 		lf_printf (file, "{\n");
 		lf_indent (file, +2);
 		lf_printf (file, "%sinstruction_address nia;\n",
@@ -860,11 +879,22 @@ gen_run_c (lf *file,
   gen_list *entry;
   lf_printf (file, "#include \"sim-main.h\"\n");
   lf_printf (file, "#include \"engine.h\"\n");
+  lf_printf (file, "#include \"idecode.h\"\n");
   lf_printf (file, "#include \"bfd.h\"\n");
   lf_printf (file, "\n");
+
+  if (options.gen.multi_sim)
+    {
+      print_idecode_issue_function_header (file, NULL, is_function_variable, 1);
+      lf_printf (file, "\n");
+      print_engine_run_function_header (file, NULL, is_function_variable);
+      lf_printf (file, "\n");
+    }
+  
   lf_printf (file, "void\n");
   lf_printf (file, "sim_engine_run (SIM_DESC sd,\n");
   lf_printf (file, "                int next_cpu_nr,\n");
+  lf_printf (file, "                int nr_cpus,\n");
   lf_printf (file, "                int siggnal)\n");
   lf_printf (file, "{\n");
   lf_indent (file, +2);
@@ -880,37 +910,62 @@ gen_run_c (lf *file,
       lf_indent (file, +2);
       for (entry = gen->tables; entry != NULL; entry = entry->next)
 	{
-	  lf_printf (file, "case bfd_mach_%s:\n", entry->processor);
+	  if (options.gen.default_model != NULL
+	      && (strcmp (entry->model->name, options.gen.default_model) == 0
+		  || strcmp (entry->model->full_name, options.gen.default_model) == 0))
+	    lf_printf (file, "default:\n");
+	  lf_printf (file, "case bfd_mach_%s:\n", entry->model->full_name);
 	  lf_indent (file, +2);
 	  print_function_name (file,
+			       "issue",
+			       NULL, /* format name */
+			       NULL, /* NO processor */
+			       NULL, /* expanded bits */
+			       function_name_prefix_idecode);
+	  lf_printf (file, " = ");
+	  print_function_name (file,
+			       "issue",
+			       NULL, /* format name */
+			       entry->model->name,
+			       NULL, /* expanded bits */
+			       function_name_prefix_idecode);
+	  lf_printf (file, ";\n");
+	  print_function_name (file,
+			       "run",
+			       NULL, /* format name */
+			       NULL, /* NO processor */
+			       NULL, /* expanded bits */
+			       function_name_prefix_engine);
+	  lf_printf (file, " = ");
+	  print_function_name (file,
 			       "run",
 			       NULL, /* format name */
-			       entry->processor,
+			       entry->model->name,
 			       NULL, /* expanded bits */
 			       function_name_prefix_engine);
-	  lf_printf (file, " (sd, next_cpu_nr, siggnal);\n");
+	  lf_printf (file, ";\n");
+	  lf_printf (file, "break;\n");
+	  lf_indent (file, -2);
+	}
+      if (options.gen.default_model == NULL)
+	{
+	  lf_printf (file, "default:\n");
+	  lf_indent (file, +2);
+	  lf_printf (file, "sim_engine_abort (sd, NULL, NULL_CIA,\n");
+	  lf_printf (file, "                  \"sim_engine_run - unknown machine\");\n");
 	  lf_printf (file, "break;\n");
 	  lf_indent (file, -2);
 	}
-      lf_printf (file, "default:\n");
-      lf_indent (file, +2);
-      lf_printf (file, "sim_engine_abort (sd, NULL, NULL_CIA,\n");
-      lf_printf (file, "                  \"sim_engine_run - unknown machine\");\n");
-      lf_printf (file, "break;\n");
-      lf_indent (file, -2);
       lf_indent (file, -2);
       lf_printf (file, "  }\n");
     }
-  else
-    {
-      print_function_name (file,
-			   "run",
-			   NULL, /* format name */
-			   NULL, /* NO processor */
-			   NULL, /* expanded bits */
-			   function_name_prefix_engine);
-      lf_printf (file, " (sd, next_cpu_nr, siggnal);\n");
-    }
+  print_function_name (file,
+		       "run",
+		       NULL, /* format name */
+		       NULL, /* NO processor */
+		       NULL, /* expanded bits */
+		       function_name_prefix_engine);
+  lf_printf (file, " (sd, next_cpu_nr, nr_cpus, siggnal);\n");
   lf_indent (file, -2);
   lf_printf (file, "}\n");
 }
@@ -1021,7 +1076,8 @@ main (int argc,
       printf ("\t gen-icache[=<N>        - generate an instruction cracking cache of size <N>\n");
       printf ("\t                          Default size is %d\n", options.gen.icache_size);
       printf ("\t gen-insn-in-icache     - save original instruction when cracking\n");
-      printf ("\t gen-multi-sim          - generate multiple simulators - one per model\n");
+      printf ("\t gen-multi-sim[=MODEL]  - generate multiple simulators - one per model\n");
+      printf ("\t                          If specified MODEL is made the default architecture.\n");
       printf ("\t                          By default, a single simulator that will\n");
       printf ("\t                          execute any instruction is generated\n");
       printf ("\t gen-multi-word         - generate code allowing for multi-word insns\n");
@@ -1292,7 +1348,8 @@ main (int argc,
 		  {
 		  case '=':
 		    options.gen.icache_size = atoi (argp + strlen ("gen-icache") + 1);
-		    /* fall through */
+		    options.gen.icache = enable_p;
+		    break;
 		  case '\0':
 		    options.gen.icache = enable_p;
 		    break;
@@ -1304,9 +1361,25 @@ main (int argc,
 	      {
 		options.gen.insn_in_icache = enable_p;
 	      }
-	    else if (strcmp (argp, "gen-multi-sim") == 0)
+	    else if (strncmp (argp, "gen-multi-sim", strlen ("gen-multi-sim")) == 0)
 	      {
-		options.gen.multi_sim = enable_p;
+		char *arg = &argp[strlen ("gen-multi-sim")];
+		switch (arg[0])
+		  {
+		  case '=':
+		    options.gen.multi_sim = enable_p;
+		    options.gen.default_model = arg + 1;
+		    if (! filter_is_member (options.model_filter, options.gen.default_model))
+		      error (NULL, "multi-sim model %s unknown\n", options.gen.default_model);
+		    break;
+		  case '\0':
+		    options.gen.multi_sim = enable_p;
+		    options.gen.default_model = NULL;
+		    break;
+		  default:
+		    error (NULL, "Expecting -Ggen-multi-sim or -Ggen-multi-sim=<MODEL>\n");
+		    break;
+		  }
 	      }
 	    else if (strcmp (argp, "gen-multi-word") == 0)
 	      {
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index e66e8d7..3ea98dd 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,12 @@
+Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* interp.c (sim_engine_run): Add `nr_cpus' argument.
+
+	* mips.igen (model): Map processor names onto BFD name.	
+
+	* sim-main.h (CPU_CIA): Delete.
+ 	(SET_CIA, GET_CIA): Define
+
 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* sim-main.h (GPR_SET): Define, used by igen when zeroing a
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index fe17645..889cc9c 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -3120,13 +3120,14 @@ decode_coproc(sd,cia,instruction)
 #if (WITH_IGEN > 1)
 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
 void
-old_engine_run (sd, next_cpu_nr, siggnal)
+old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
 #else
 void
-sim_engine_run (sd, next_cpu_nr, siggnal)
+sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
 #endif
      SIM_DESC sd;
      int next_cpu_nr; /* ignore */
+     int nr_cpus; /* ignore */
      int siggnal; /* ignore */
 {
 #if !defined(FASTSIM)
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 201564b..1f56c78 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -289,7 +289,8 @@ struct _sim_cpu {
 
 
   /* The following are internal simulator state variables: */
-#define CPU_CIA(CPU) (PC)
+#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
+#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
   address_word dspc;  /* delay-slot PC */
 #define DSPC ((STATE_CPU (sd,0))->dspc)
 
@@ -378,7 +379,8 @@ struct _sim_cpu {
 #define FGR     (&REGISTERS[FGRIDX])
 #define LO      (REGISTERS[33])
 #define HI      (REGISTERS[34])
-#define PC      (REGISTERS[37])
+#define PCIDX	37
+#define PC      (REGISTERS[PCIDX])
 #define CAUSE   (REGISTERS[36])
 #define SRIDX   (32)
 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog
index 0405124..d0a2f97 100644
--- a/sim/tic80/ChangeLog
+++ b/sim/tic80/ChangeLog
@@ -1,3 +1,8 @@
+Fri Jan 30 11:47:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* cpu.h (CPU_CIA): Delete macro, replace with...
+ 	(CIA_SET, CIA_GET): Define.
+
 Wed Jan 28 18:44:33 1998  Michael Meissner  <meissner@cygnus.com>
 
 	* misc.c (tic80_trace_cmp_internal): New function to return
diff --git a/sim/tic80/cpu.h b/sim/tic80/cpu.h
index 4124512..6801c04 100644
--- a/sim/tic80/cpu.h
+++ b/sim/tic80/cpu.h
@@ -151,7 +151,8 @@ struct _sim_cpu {
   sim_cpu_base base;
 };
 
-#define CPU_CIA(CPU) ((CPU)->cia)
+#define CIA_GET(CPU) ((CPU)->cia)
+#define CIA_SET(CPU,VAL) ((CPU)->cia = (VAL))
 
 #define GPR(N) ((CPU)->reg[N])
 #define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL))
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 43e7956..e0594a8 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,8 @@
+Fri Jan 30 09:51:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* sim-main.h (CPU_CIA): Delete, replaced by.
+	(CIA_SET, CIA_SET): Define.
+
 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
 
 	* configure: Regenerated to track ../common/aclocal.m4 changes.