From: Rohan Garg <rohan.garg@intel.com>
Date: Fri, 8 Sep 2023 15:10:37 +0000 (+0200)
Subject: intel/genxml: update PIPE_CONTROL instruction for dg2
X-Git-Tag: upstream/23.3.3~2109
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9eba1d918757d741ade4d88435978d195a19a052;p=platform%2Fupstream%2Fmesa.git

intel/genxml: update PIPE_CONTROL instruction for dg2

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25124>
---

diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index f274a27..ba5e24e 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -6543,6 +6543,7 @@
     <field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool" />
     <field name="Untyped Data Port Cache Flush Enable" start="11" end="11" type="bool" />
     <field name="CCS Flush Enable" start="13" end="13" type="bool" />
+    <field name="Workload Partition ID Offset Enable" start="14" end="14" type="bool" />
     <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0" />
     <field name="3D Command Opcode" start="24" end="26" type="uint" default="2" />
     <field name="Command SubType" start="27" end="28" type="uint" default="3" />
@@ -6553,6 +6554,7 @@
     <field name="Constant Cache Invalidation Enable" start="35" end="35" type="bool" />
     <field name="VF Cache Invalidation Enable" start="36" end="36" type="bool" />
     <field name="DC Flush Enable" start="37" end="37" type="bool" />
+    <field name="Protected Memory Application ID" start="38" end="38" type="bool" />
     <field name="Pipe Control Flush Enable" start="39" end="39" type="bool" />
     <field name="Notify Enable" start="40" end="40" type="bool" />
     <field name="Indirect State Pointers Disable" start="41" end="41" type="bool" />
@@ -6569,6 +6571,7 @@
     <field name="Generic Media State Clear" start="48" end="48" type="bool" />
     <field name="PSS Stall Sync Enable" start="49" end="49" type="bool" />
     <field name="TLB Invalidate" start="50" end="50" type="bool" />
+    <field name="Depth Stall Sync Enable" start="51" end="51" type="bool" />
     <field name="Command Streamer Stall Enable" start="52" end="52" type="bool" />
     <field name="Store Data Index" start="53" end="53" type="uint" />
     <field name="Protected Memory Enable" start="54" end="54" type="bool" />
@@ -6580,10 +6583,15 @@
       <value name="PPGTT" value="0" />
       <value name="GGTT" value="1" />
     </field>
+    <field name="AMFS Flush Enable" start="57" end="57" type="bool" />
     <field name="Flush LLC" start="58" end="58" type="bool" />
     <field name="Protected Memory Disable" start="59" end="59" type="bool" />
     <field name="Tile Cache Flush Enable" start="60" end="60" type="bool" />
     <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool" />
+    <field name="TBIMR Force Batch Closure" start="63" end="63" type="uint">
+      <value name="No Batch Closure" value="0" />
+      <value name="Close Batch" value="1" />
+    </field>
     <field name="Address" start="66" end="111" type="address" />
     <field name="Immediate Data" start="128" end="191" type="uint" />
   </instruction>