From: Donghwa Lee Date: Mon, 13 Sep 2010 06:16:52 +0000 (+0900) Subject: s5p: mipi: fixed the bug X-Git-Tag: JI01_20100913~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9e9538cf3f98b88dc5b422fb91d939aae56ac703;p=kernel%2Fu-boot.git s5p: mipi: fixed the bug --- diff --git a/arch/arm/include/asm/arch-s5pc2xx/regs-dsim.h b/arch/arm/include/asm/arch-s5pc2xx/regs-dsim.h new file mode 100644 index 0000000..57b86e2 --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc2xx/regs-dsim.h @@ -0,0 +1,302 @@ +/* linux/asm/arch/regs-dsim.h + * + * Register definition file for MIPI-DSI driver + * + * Donghwa Lee, Copyright (c) 2010 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S5P_DSIMREG(x) (x) + +#define S5P_DSIM_STATUS S5P_DSIMREG(0x0000) +#define S5P_DSIM_SWRST S5P_DSIMREG(0x0004) +#define S5P_DSIM_CLKCTRL S5P_DSIMREG(0x0008) +#define S5P_DSIM_TIMEOUT S5P_DSIMREG(0x000C) +#define S5P_DSIM_CONFIG S5P_DSIMREG(0x0010) +#define S5P_DSIM_ESCMODE S5P_DSIMREG(0x0014) +#define S5P_DSIM_MDRESOL S5P_DSIMREG(0x0018) +#define S5P_DSIM_MVPORCH S5P_DSIMREG(0x001C) +#define S5P_DSIM_MHPORCH S5P_DSIMREG(0x0020) +#define S5P_DSIM_MSYNC S5P_DSIMREG(0x0024) +#define S5P_DSIM_SDRESOL S5P_DSIMREG(0x0028) +#define S5P_DSIM_INTSRC S5P_DSIMREG(0x002C) +#define S5P_DSIM_INTMSK S5P_DSIMREG(0x0030) +#define S5P_DSIM_PKTHDR S5P_DSIMREG(0x0034) +#define S5P_DSIM_PAYLOAD S5P_DSIMREG(0x0038) +#define S5P_DSIM_RXFIFO S5P_DSIMREG(0x003C) +#define S5P_DSIM_FIFOTHLD S5P_DSIMREG(0x0040) +#define S5P_DSIM_FIFOCTRL S5P_DSIMREG(0x0044) +#define S5P_DSIM_MEMACCHR S5P_DSIMREG(0x0048) +#define S5P_DSIM_PLLCTRL S5P_DSIMREG(0x004C) +#define S5P_DSIM_PLLTMR S5P_DSIMREG(0x0050) +#define S5P_DSIM_PHYACCHR S5P_DSIMREG(0x0054) +#define S5P_DSIM_PHYACCHR1 S5P_DSIMREG(0x0058) + + +/* + * Bit Definitions +*/ +#define DSIM_STATUS_PLLSTABLE (0 << 31) +#define DSIM_STATUS_SWRSTRLS (1 << 20) +#define DSIM_STATUS_SWRSTRST (0 << 20) +#define DSIM_STATUS_DIRECTION_B (1 << 16) +#define DSIM_STATUS_DIRECTION_F (0 << 16) +#define DSIM_STATUS_TX_READY_HSCLK (1 << 10) +#define DSIM_STATUS_TX_NOTREADY_HSCLK (1 << 10) +#define DSIM_STATUS_ULPSCLK (1 << 9) +#define DSIM_STATUS_NOULPSCLK (0 << 9) +#define DSIM_STATUS_STOP_STATECLK (0 << 8) +#define DSIM_STATUS_NOSTOP_STATECLK (0 << 8) +#define DSIM_STATUS_ULPSDAT(x) (((x) & 0xf) << 4) +#define DSIM_STATUS_STOP_STATEDAT(x) ((x) & 0xf) + +#define DSIM_SWRST_FUNCRST_STANDBY (0 << 16) +#define DSIM_SWRST_FUNCRST_RESET (1 << 16) +#define DSIM_SWRST_SWRST_STANDBY (0 << 0) +#define DSIM_SWRST_SWRST_RESET (1 << 0) + +/* S5P_DSIM_TIMEOUT */ +#define DSIM_LPDR_TOUT_SHIFT (0) +#define DSIM_BTA_TOUT_SHIFT (16) +#define DSIM_LPDR_TOUT(x) (((x) & 0xffff) << DSIM_LPDR_TOUT_SHIFT) +#define DSIM_BTA_TOUT(x) (((x) & 0xff) << DSIM_BTA_TOUT_SHIFT) + +/* S5P_DSIM_CLKCTRL */ +#define DSIM_ESC_PRESCALER_SHIFT (0) +#define DSIM_LANE_ESC_CLKEN_SHIFT (19) +#define DSIM_BYTE_CLKEN_SHIFT (24) +#define DSIM_BYTE_CLK_SRC_SHIFT (25) +#define DSIM_PLL_BYPASS_SHIFT (27) +#define DSIM_ESC_CLKEN_SHIFT (28) +#define DSIM_TX_REQUEST_HSCLK_SHIFT (31) +#define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << \ + DSIM_ESC_PRESCALER_SHIFT) +#define DSIM_LANE_ESC_CLKEN(x) (((x) & 0x1f) << \ + DSIM_LANE_ESC_CLKEN_SHIFT) +#define DSIM_BYTE_CLK_ENABLE (1 << DSIM_BYTE_CLKEN_SHIFT) +#define DSIM_BYTE_CLK_DISABLE (0 << DSIM_BYTE_CLKEN_SHIFT) +#define DSIM_BYTE_CLKSRC(x) (((x) & 0x3) << DSIM_BYTE_CLK_SRC_SHIFT) +#define DSIM_PLL_BYPASS_PLL (0 << DSIM_PLL_BYPASS_SHIFT) +#define DSIM_PLL_BYPASS_EXTERNAL (1 << DSIM_PLL_BYPASS_SHIFT) +#define DSIM_ESC_CLKEN_ENABLE (1 << DSIM_ESC_CLKEN_SHIFT) +#define DSIM_ESC_CLKEN_DISABLE (0 << DSIM_ESC_CLKEN_SHIFT) + +#define DSIM_TIMEOUT_BTATOUT(x) (((x) & 0xff) << 16) +#define DSIM_TIMEOUT_LPDRTOUT(x) (((x) & 0xffff) << 0) + +/* S5P_DSIM_CONFIG */ +#define DSIM_LANE_EN_SHIFT (0) +#define DSIM_NUM_OF_DATALANE_SHIFT (5) +#define DSIM_SUB_PIX_FORMAT_SHIFT (8) +#define DSIM_MAIN_PIX_FORMAT_SHIFT (12) +#define DSIM_SUB_VC_SHIFT (16) +#define DSIM_MAIN_VC_SHIFT (18) +#define DSIM_HSA_MODE_SHIFT (20) +#define DSIM_HBP_MODE_SHIFT (21) +#define DSIM_HFP_MODE_SHIFT (22) +#define DSIM_HSE_MODE_SHIFT (23) +#define DSIM_AUTO_MODE_SHIFT (24) +#define DSIM_VIDEO_MODE_SHIFT (25) +#define DSIM_BURST_MODE_SHIFT (26) +#define DSIM_SYNC_INFORM_SHIFT (27) +#define DSIM_EOT_R03_SHIFT (28) +#define DSIM_LANE_ENx(x) ((1) << x) + +/* in case of Gemunus, it should be 0x1. */ +#define DSIM_NUM_OF_DATA_LANE(x) ((x) << 5) +#define DSIM_SUB_PIX_FORMAT_3BPP (0 << 8) /* command mode only */ +#define DSIM_SUB_PIX_FORMAT_8BPP (1 << 8) /* command mode only */ +#define DSIM_SUB_PIX_FORMAT_12BPP (2 << 8) /* command mode only */ +#define DSIM_SUB_PIX_FORMAT_16BPP (3 << 8) /* command mode only */ +#define DSIM_SUB_PIX_FORMAT_16BPP_RGB (4 << 8) /* video mode only */ +#define DSIM_SUB_PIX_FORMAT_18BPP_PRGB (5 << 8) /* video mode only */ +#define DSIM_SUB_PIX_FORMAT_18BPP_LRGB (6 << 8) /* common */ +#define DSIM_SUB_PIX_FORMAT_24BPP_RGB (7 << 8) /* common */ +#define DSIM_MAIN_PIX_FORMAT_3BPP (0 << 12) /* command mode only */ +#define DSIM_MAIN_PIX_FORMAT_8BPP (1 << 12) /* command mode only */ +#define DSIM_MAIN_PIX_FORMAT_12BPP (2 << 12) /* command mode only */ +#define DSIM_MAIN_PIX_FORMAT_16BPP (3 << 12) /* command mode only */ +#define DSIM_MAIN_PIX_FORMAT_16BPP_RGB (4 << 12) /* video mode only */ +#define DSIM_MAIN_PIX_FORMAT_18BPP_PRGB (5 << 12) /* video mode only */ +#define DSIM_MAIN_PIX_FORMAT_18BPP_LRGB (6 << 12) /* common */ +#define DSIM_MAIN_PIX_FORMAT_24BPP_RGB (7 << 12) /* common */ + +/* Virtual channel number for sub display */ +#define DSIM_SUB_VC(x) (((x) & 0x3) << 16) +/* Virtual channel number for main display */ +#define DSIM_MAIN_VC(x) (((x) & 0x3) << 18) +#define DSIM_HSA_MODE_ENABLE (1 << 20) +#define DSIM_HSA_MODE_DISABLE (0 << 20) +#define DSIM_HBP_MODE_ENABLE (1 << 21) +#define DSIM_HBP_MODE_DISABLE (0 << 21) +#define DSIM_HFP_MODE_ENABLE (1 << 22) +#define DSIM_HFP_MODE_DISABLE (0 << 22) +#define DSIM_HSE_MODE_ENABLE (1 << 23) +#define DSIM_HSE_MODE_DISABLE (0 << 23) +#define DSIM_AUTO_MODE (1 << 24) +#define DSIM_CONFIGURATION_MODE (0 << 24) +#define DSIM_VIDEO_MODE (1 << 25) +#define DSIM_COMMAND_MODE (0 << 25) +#define DSIM_BURST_MODE (1 << 26) +#define DSIM_NON_BURST_MODE (0 << 26) +#define DSIM_SYNC_INFORM_PULSE (1 << 27) +#define DSIM_SYNC_INFORM_EVENT (0 << 27) +/* enable EoT packet generation for V1.01r11 */ +#define DSIM_EOT_R03_ENABLE (0 << 28) +/* disable EoT packet generation for V1.01r03 */ +#define DSIM_EOT_R03_DISABLE (1 << 28) + +/* S5P_DSIM_MHPORCH */ +#define DSIM_MAIN_HFP_SHIFT (16) +#define DSIM_MAIN_HBP_SHIFT (0) +#define DSIM_MAIN_HFP_MASK ((0xffff) << DSIM_MAIN_HFP_SHIFT) +#define DSIM_MAIN_HBP_MASK ((0xffff) << DSIM_MAIN_HBP_SHIFT) +#define DSIM_MAIN_HFP(x) (((x) & 0xffff) << DSIM_MAIN_HFP_SHIFT) +#define DSIM_MAIN_HBP(x) (((x) & 0xffff) << DSIM_MAIN_HBP_SHIFT) + +/* S5P_DSIM_MSYNC */ +#define DSIM_MAIN_VSA_SHIFT (22) +#define DSIM_MAIN_HSA_SHIFT (0) +#define DSIM_MAIN_VSA_MASK ((0x3ff) << DSIM_MAIN_VSA_SHIFT) +#define DSIM_MAIN_HSA_MASK ((0xffff) << DSIM_MAIN_HSA_SHIFT) +#define DSIM_MAIN_VSA(x) (((x) & 0x3ff) << DSIM_MAIN_VSA_SHIFT) +#define DSIM_MAIN_HSA(x) (((x) & 0xffff) << DSIM_MAIN_HSA_SHIFT) + +/* S5P_DSIM_ESCMODE */ +#define DSIM_STOP_STATE_CNT_SHIFT (21) +#define DSIM_STOP_STATE_CNT(x) (((x) & 0x3ff) << \ + DSIM_STOP_STATE_CNT_SHIFT) +#define DSIM_FORCE_STOP_STATE_SHIFT (20) +#define DSIM_FORCE_BTA_SHIFT (16) +#define DSIM_CMD_LPDT_HS_MODE (0 << 7) +#define DSIM_CMD_LPDT_LP_MODE (1 << 7) +#define DSIM_TX_LPDT_HS_MODE (0 << 6) +#define DSIM_TX_LPDT_LP_MODE (1 << 6) +#define DSIM_TX_TRIGGER_RST_SHIFT (4) +#define DSIM_TX_UIPS_DAT_SHIFT (3) +#define DSIM_TX_UIPS_EXIT_SHIFT (2) +#define DSIM_TX_UIPS_CLK_SHIFT (1) +#define DSIM_TX_UIPS_CLK_EXIT_SHIFT (0) + +/* S5P_DSIM_MDRESOL */ +#define DSIM_MDRESOL_MAIN_NOT_STANDBY (0 << 31) +#define DSIM_MDRESOL_MAIN_STAND_BY (1 << 31) +#define DSIM_MDRESOL_MAIN_VRESOL(x) (((x) & 0x7ff) << 16) +#define DSIM_MDRESOL_MAIN_HRESOL(x) (((x) & 0x7ff) << 0) + +/* S5P_DSIM_MVPORCH */ +#define DSIM_CMD_ALLOW_SHIFT (28) +#define DSIM_STABLE_VFP_SHIFT (16) +#define DSIM_MAIN_VBP_SHIFT (0) +#define DSIM_CMD_ALLOW_MASK (0xf << DSIM_CMD_ALLOW_SHIFT) +#define DSIM_STABLE_VFP_MASK (0x7ff << DSIM_STABLE_VFP_SHIFT) +#define DSIM_MAIN_VBP_MASK (0x7ff << DSIM_MAIN_VBP_SHIFT) +#define DSIM_CMD_ALLOW(x) (((x) & 0xf) << DSIM_CMD_ALLOW_SHIFT) +#define DSIM_STABLE_VFP(x) (((x) & 0x7ff) << DSIM_STABLE_VFP_SHIFT) +#define DSIM_MAIN_VBP(x) (((x) & 0x7ff) << DSIM_MAIN_VBP_SHIFT) + +/* S5P_DSIM_MHPORCH */ +#define DSIM_MHPORCH_MAIN_HFP(x) (((x) & 0xffff) << 16) +#define DSIM_MHPORCH_MAIN_HBP(x) (((x) & 0xffff) << 0) + + +#define DSIM_MSYNC_MAIN_VSA(x) (((x) & 0x3ff) << 22) +#define DSIM_MSYNC_MAIN_HSA(x) (((x) & 0xffff) << 0) + +/* S5P_DSIM_SDRESOL */ +#define DSIM_SUB_STANDY_SHIFT (31) +#define DSIM_SUB_VRESOL_SHIFT (16) +#define DSIM_SUB_HRESOL_SHIFT (0) +#define DSIM_SUB_STANDY_MASK ((0x1) << DSIM_SUB_STANDY_SHIFT) +#define DSIM_SUB_VRESOL_MASK ((0x7ff) << DSIM_SUB_VRESOL_SHIFT) +#define DSIM_SUB_HRESOL_MASK ((0x7ff) << DSIM_SUB_HRESOL_SHIFT) +#define DSIM_SUB_STANDY (1 << DSIM_SUB_STANDY_SHIFT) +#define DSIM_SUB_NOT_READY (0 << DSIM_SUB_STANDY_SHIFT) +#define DSIM_SUB_VRESOL(x) (((x) & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) +#define DSIM_SUB_HRESOL(x) (((x) & 0x7ff) << DSIM_SUB_HRESOL_SHIFT) + + +#define DSIM_INTSRC_PLL_STABLE (1 << 31) +#define DSIM_INTSRC_SW_RST_RELEASE (1 << 30) +#define DSIM_INTSRC_SFR_FIFO_EMPTY (1 << 29) +#define DSIM_INTSRC_SYNC_OVERRIDE (1 << 28) +#define DSIM_INTSRC_BUS_TURN_OVER (1 << 25) +#define DSIM_INTSRC_FRAME_DONE (1 << 24) +#define DSIM_INTSRC_LPDRTOUT (1 << 21) +#define DSIM_INTSRC_TATOUT (1 << 20) +#define DSIM_INTSRC_RX_DAT_DONE (1 << 18) +#define DSIM_INTSRC_RX_TE (1 << 17) +#define DSIM_INTSRC_RX_ACK (1 << 16) +#define DSIM_INTSRC_ERR_RX_ECC (1 << 15) +#define DSIM_INTSRC_ERR_RX_CRC (1 << 14) +#define DSIM_INTSRC_ERR_ESC3 (1 << 13) +#define DSIM_INTSRC_ERR_ESC2 (1 << 12) +#define DSIM_INTSRC_ERR_ESC1 (1 << 11) +#define DSIM_INTSRC_ERR_ESC0 (1 << 10) +#define DSIM_INTSRC_ERR_SYNC3 (1 << 9) +#define DSIM_INTSRC_ERR_SYNC2 (1 << 8) +#define DSIM_INTSRC_ERR_SYNC1 (1 << 7) +#define DSIM_INTSRC_ERR_SYNC0 (1 << 6) +#define DSIM_INTSRC_ERR_CONTROL3 (1 << 5) +#define DSIM_INTSRC_ERR_CONTROL2 (1 << 4) +#define DSIM_INTSRC_ERR_CONTROL1 (1 << 3) +#define DSIM_INTSRC_ERR_CONTROL0 (1 << 2) +#define DSIM_INTSRC_ERR_CONTENT_LP0 (1 << 1) +#define DSIM_INTSRC_ERR_CONTENT_LP1 (1 << 0) + +#define DSIM_INTMSK_ERR_CONTENT_LP1 (1 << 0) +#define DSIM_INTMSK_ERR_CONTENT_LP0 (1 << 1) +#define DSIM_INTMSK_ERR_CONTROL0 (1 << 2) +#define DSIM_INTMSK_ERR_CONTROL1 (1 << 3) +#define DSIM_INTMSK_ERR_CONTROL2 (1 << 4) +#define DSIM_INTMSK_ERR_CONTROL3 (1 << 5) +#define DSIM_INTMSK_ERR_SYNC0 (1 << 6) +#define DSIM_INTMSK_ERR_SYNC1 (1 << 7) +#define DSIM_INTMSK_ERR_SYNC2 (1 << 8) +#define DSIM_INTMSK_ERR_SYNC3 (1 << 9) +#define DSIM_INTMSK_ERR_ESC0 (1 << 10) +#define DSIM_INTMSK_ERR_ESC1 (1 << 11) +#define DSIM_INTMSK_ERR_ESC2 (1 << 12) +#define DSIM_INTMSK_ERR_ESC3 (1 << 13) +#define DSIM_INTMSK_ERR_RX_CRC (1 << 14) +#define DSIM_INTMSK_ERR_RX_ECC (1 << 15) +#define DSIM_INTMSK_RX_ACK (1 << 16) +#define DSIM_INTMSK_RX_TE (1 << 17) +#define DSIM_INTMSK_RX_DAT_DONE (1 << 18) +#define DSIM_INTMSK_TA_TOUT (1 << 20) +#define DSIM_INTMSK_LPDR_TOUT (1 << 21) +#define DSIM_INTMSK_FRAME_DONE (1 << 24) +#define DSIM_INTMSK_BUS_TURN_OVER (1 << 25) +#define DSIM_INTMSK_SFR_FIFO_EMPTY (1 << 29) +#define DSIM_INTMSK_SW_RST_RELEASE (1 << 30) +#define DSIM_INTMSK_PLL_STABLE (1 << 31) + +#define DSIM_PKTHDR_HEADER_DI(x) (((x) & 0xff) << 0) +#define DSIM_PKTHDR_HEADER_DAT0(x) (((x) & 0xff) << 8) +#define DSIM_PKTHDR_HEADER_DAT1(x) (((x) & 0xff) << 16) + +/* S5P_DSIM_PHYACCHR */ +#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) +#define DSIM_AFC_ENABLE (1 << 14) +#define DSIM_AFC_DISABLE (0 << 14) + +#define DSIM_RX_FIFO (1 << 4) +#define DSIM_TX_SFR_FIFO (1 << 3) +#define DSIM_I80_FIFO (1 << 2) +#define DSIM_SUB_DISP_FIFO (1 << 1) +#define DSIM_MAIN_DISP_FIFO (1 << 0) + +/* S5P_DSIM_PLLCTRL */ +#define DSIM_PMS_SHIFT (1) +#define DSIM_PLL_EN_SHIFT (23) +#define DSIM_FREQ_BAND_SHIFT (24) +#define DSIM_PMS(x) (((x) & 0x7ffff) << DSIM_PMS_SHIFT) +#define DSIM_FREQ_BAND(x) (((x) & 0xf) << DSIM_FREQ_BAND_SHIFT) + +/* DSIM_SWRST */ +#define DSIM_FUNCRST (1 << 16) +#define DSIM_SWRST (1 << 0) + diff --git a/arch/arm/include/asm/arch-s5pc2xx/regs-fb.h b/arch/arm/include/asm/arch-s5pc2xx/regs-fb.h index 593eb08..4a9a66b 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/regs-fb.h +++ b/arch/arm/include/asm/arch-s5pc2xx/regs-fb.h @@ -121,6 +121,12 @@ #define S5P_WPALCON_H S5P_LCDREG(0x019C) /* Window Palette control */ #define S5P_WPALCON_L S5P_LCDREG(0x01A0) /* Window Palette control */ +#define S5P_TRIGCON S5P_LCDREG(0x01A4) /* I80/RGB Trigger control */ +#define S5P_I80IFCONA0 S5P_LCDREG(0x01B0) /* I80 interface control 0 for main LDI */ +#define S5P_I80IFCONA1 S5P_LCDREG(0x01B4) /* I80 interface control 0 for main LDI */ +#define S5P_I80IFCONB0 S5P_LCDREG(0x01B8) /* I80 interface control 0 for main LDI */ +#define S5P_I80IFCONB1 S5P_LCDREG(0x01B8) /* I80 interface control 0 for main LDI */ + #define S5P_VIDW0ALPHA0 S5P_LCDREG(0x0200) /* Window 0 alpha value 0 */ #define S5P_VIDW0ALPHA1 S5P_LCDREG(0x0204) /* Window 0 alpha value 1 */ #define S5P_VIDW1ALPHA0 S5P_LCDREG(0x0208) /* Window 1 alpha value 0 */ @@ -386,4 +392,13 @@ #define S5P_DUALRGB_VDEN_EN_ENABLE (0x1 << 16) #define S5P_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18) +/* I80IFCONA0 and I80IFCONA1 */ +#define S5C_LCD_CS_SETUP(x) (((x) & 0xf) << 16) +#define S5C_LCD_WR_SETUP(x) (((x) & 0xf) << 12) +#define S5C_LCD_WR_ACT(x) (((x) & 0xf) << 8) +#define S5C_LCD_WR_HOLD(x) (((x) & 0xf) << 4) +#define S5C_RSPOL_LOW (0 << 2) +#define S5C_RSPOL_HIGH (1 << 2) +#define S5C_I80IFEN_DISABLE (0 << 0) +#define S5C_I80IFEN_ENABLE (1 << 0) #endif /* _REGS_FB_H */ diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 6f0f504..064509f 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -797,6 +797,7 @@ void init_panel_info(vidinfo_t *vid) vid->init_delay = 0; vid->power_on_delay = 30000; vid->reset_delay = 20000; + vid->interface_mode = FIMD_RGB_INTERFACE; } static unsigned short get_adc_value(int channel) diff --git a/drivers/video/s5p-dsim.c b/drivers/video/s5p-dsim.c index 9b3ffcc..9dce5fb 100644 --- a/drivers/video/s5p-dsim.c +++ b/drivers/video/s5p-dsim.c @@ -13,8 +13,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -771,11 +771,11 @@ int s5p_dsim_enable_d_phy(struct dsim_global *dsim, unsigned int enable) udebug("dsim is NULL.\n"); return -EFAULT; } - +#ifdef CONFIG_S5PC110 reg = (readl(S5PC110_MIPI_DPHY_CONTROL)) & ~(1 << 0); reg |= (enable << 0); writel(reg, S5PC110_MIPI_DPHY_CONTROL); - +#endif return 0; } @@ -790,10 +790,11 @@ int s5p_dsim_enable_dsi_master(struct dsim_global *dsim, return -EFAULT; } +#ifdef CONFIG_S5PC110 reg = (readl(S5PC110_MIPI_DPHY_CONTROL)) & ~(1 << 2); reg |= (enable << 2); writel(reg, S5PC110_MIPI_DPHY_CONTROL); - +#endif return 0; } diff --git a/drivers/video/s5p-fimd.c b/drivers/video/s5p-fimd.c index 404004f..1d4a3e7b 100644 --- a/drivers/video/s5p-fimd.c +++ b/drivers/video/s5p-fimd.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include "s5p-fb.h" @@ -309,6 +309,7 @@ int s5pc_set_auto_cmd_rate(unsigned char cmd_rate, unsigned char ldi) return 0; } + void s5pc_fimd_lcd_init(vidinfo_t *vid) { unsigned int cfg = 0, rgb_mode, win_id = 3; diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 426193a..36878c9 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -359,6 +359,7 @@ #define CONFIG_S6E63M0 1 #define CONFIG_S6D16A0X 1 #define CONFIG_LD9040 1 +#define CONFIG_DSIM 1 #define CONFIG_CMD_BMP #endif diff --git a/include/dsim.h b/include/dsim.h index 272df9d..d04828a 100644 --- a/include/dsim.h +++ b/include/dsim.h @@ -10,7 +10,7 @@ * published by the Free Software Foundation. */ -#include +#include #include #define DEBUG diff --git a/include/mipi_ddi.h b/include/mipi_ddi.h new file mode 100644 index 0000000..7895f3e --- /dev/null +++ b/include/mipi_ddi.h @@ -0,0 +1,88 @@ +/* linux/arm/arch/mach-s5pc110/include/mach/mipi_ddi.h + * + * definitions for DDI based MIPI-DSI. + * + * Copyright (c) 2009 Samsung Electronics + * InKi Dae + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _MIPI_DDI_H +#define _MIPI_DDI_H + +enum mipi_ddi_interface { + RGB_IF = 0x4000, + I80_IF = 0x8000, + YUV_601 = 0x10000, + YUV_656 = 0x20000, + MIPI_VIDEO = 0x1000, + MIPI_COMMAND = 0x2000, +}; + +enum mipi_ddi_panel_select { + DDI_MAIN_LCD = 0, + DDI_SUB_LCD = 1, +}; + +enum mipi_ddi_model { + S6DR117 = 0, +}; + +enum mipi_ddi_parameter { + /* DSIM video interface parameter */ + DSI_VIRTUAL_CH_ID = 0, + DSI_FORMAT = 1, + DSI_VIDEO_MODE_SEL = 2, +}; + +struct lcd_device; + +struct mipi_ddi_platform_data { + void *dsim_data; + /* + * it is used for command mode lcd panel and + * when all contents of framebuffer in panel module are transfered + * to lcd panel it occurs te signal. + * + * note: + * - in case of command mode(cpu mode), it should be triggered only + * when TE signal of lcd panel and frame done interrupt of display + * controller or mipi controller occurs. + */ + unsigned int te_irq; + + /* + * it is used for PM stable time at te interrupt handler and + * could be used according to lcd panel characteristic or not. + */ + unsigned int resume_complete; + /* transfer command to lcd panel at LP mode. */ + int (*cmd_write) (void *dsim_data, unsigned int data_id, + unsigned int data0, unsigned int data1); + int (*cmd_read) (void *dsim_data, unsigned int data_id, + unsigned int data0, unsigned int data1); + /* + * get the status that all screen data have been transferred + * to mipi-dsi. + */ + int (*get_dsim_frame_done) (void *dsim_data); + int (*clear_dsim_frame_done) (void *dsim_data); + + /* + * changes mipi transfer mode to LP or HS mode. + * + * LP mode needs when some commands like gamma values transfers + * to lcd panel. + */ + int (*change_dsim_transfer_mode) (int mode); + + /* get frame done status of display controller. */ + int (*get_fb_frame_done) (void); + /* trigger display controller in case of cpu mode. */ + void (*trigger) (void); +}; + +#endif /* _MIPI_DDI_H */