From: Samuel Pitoiset Date: Wed, 3 May 2023 06:36:54 +0000 (+0200) Subject: radv: use vk_image::extent instead of radv_image::info::{width,height,depth} X-Git-Tag: upstream/23.3.3~9025 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9e846ab1dccc5b40544547ae66cecc58b7e5d229;p=platform%2Fupstream%2Fmesa.git radv: use vk_image::extent instead of radv_image::info::{width,height,depth} Signed-off-by: Samuel Pitoiset Part-of: --- diff --git a/src/amd/vulkan/meta/radv_meta_blit.c b/src/amd/vulkan/meta/radv_meta_blit.c index 1f26838..908c0a2 100644 --- a/src/amd/vulkan/meta/radv_meta_blit.c +++ b/src/amd/vulkan/meta/radv_meta_blit.c @@ -199,11 +199,11 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, VkRect2D dst_box, VkSampler sampler) { struct radv_device *device = cmd_buffer->device; - uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->vk.base_mip_level); - uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->vk.base_mip_level); - uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->vk.base_mip_level); - uint32_t dst_width = radv_minify(dst_iview->image->info.width, dst_iview->vk.base_mip_level); - uint32_t dst_height = radv_minify(dst_iview->image->info.height, dst_iview->vk.base_mip_level); + uint32_t src_width = radv_minify(src_iview->image->vk.extent.width, src_iview->vk.base_mip_level); + uint32_t src_height = radv_minify(src_iview->image->vk.extent.height, src_iview->vk.base_mip_level); + uint32_t src_depth = radv_minify(src_iview->image->vk.extent.depth, src_iview->vk.base_mip_level); + uint32_t dst_width = radv_minify(dst_iview->image->vk.extent.width, dst_iview->vk.base_mip_level); + uint32_t dst_height = radv_minify(dst_iview->image->vk.extent.height, dst_iview->vk.base_mip_level); assert(src_image->vk.samples == dst_image->vk.samples); diff --git a/src/amd/vulkan/meta/radv_meta_bufimage.c b/src/amd/vulkan/meta/radv_meta_bufimage.c index 1d1d736..34af76c 100644 --- a/src/amd/vulkan/meta/radv_meta_bufimage.c +++ b/src/amd/vulkan/meta/radv_meta_bufimage.c @@ -1766,7 +1766,7 @@ radv_meta_clear_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, device->meta_state.cleari_r32g32b32.img_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); - radv_unaligned_dispatch(cmd_buffer, dst->image->info.width, dst->image->info.height, 1); + radv_unaligned_dispatch(cmd_buffer, dst->image->vk.extent.width, dst->image->vk.extent.height, 1); radv_buffer_view_finish(&dst_view); radv_DestroyBuffer(radv_device_to_handle(device), buffer, NULL); @@ -1834,7 +1834,7 @@ radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_bl device->meta_state.cleari.img_p_layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, push_constants); - radv_unaligned_dispatch(cmd_buffer, dst->image->info.width, dst->image->info.height, 1); + radv_unaligned_dispatch(cmd_buffer, dst->image->vk.extent.width, dst->image->vk.extent.height, 1); radv_image_view_finish(&dst_iview); } diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index acef6a7..9fe4bbc 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -789,8 +789,8 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_ return false; if (clear_rect->rect.offset.x || clear_rect->rect.offset.y || - clear_rect->rect.extent.width != iview->image->info.width || - clear_rect->rect.extent.height != iview->image->info.height) + clear_rect->rect.extent.width != iview->image->vk.extent.width || + clear_rect->rect.extent.height != iview->image->vk.extent.height) return false; if (view_mask && (iview->image->vk.array_layers >= 32 || @@ -1361,8 +1361,8 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer, if (!radv_dcc_enabled(image, range->baseMipLevel + l)) continue; - width = radv_minify(image->info.width, range->baseMipLevel + l); - height = radv_minify(image->info.height, range->baseMipLevel + l); + width = radv_minify(image->vk.extent.width, range->baseMipLevel + l); + height = radv_minify(image->vk.extent.height, range->baseMipLevel + l); radv_image_view_init( &iview, cmd_buffer->device, @@ -1727,8 +1727,8 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_ return false; if (clear_rect->rect.offset.x || clear_rect->rect.offset.y || - clear_rect->rect.extent.width != iview->image->info.width || - clear_rect->rect.extent.height != iview->image->info.height) + clear_rect->rect.extent.width != iview->image->vk.extent.width || + clear_rect->rect.extent.height != iview->image->vk.extent.height) return false; if (view_mask && (iview->image->vk.array_layers >= 32 || @@ -2024,8 +2024,8 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *im const VkClearValue *clear_val) { struct radv_image_view iview; - uint32_t width = radv_minify(image->info.width, range->baseMipLevel + level); - uint32_t height = radv_minify(image->info.height, range->baseMipLevel + level); + uint32_t width = radv_minify(image->vk.extent.width, range->baseMipLevel + level); + uint32_t height = radv_minify(image->vk.extent.height, range->baseMipLevel + level); radv_image_view_init(&iview, cmd_buffer->device, &(VkImageViewCreateInfo){ @@ -2126,8 +2126,8 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima .offset = {0, 0}, .extent = { - radv_minify(image->info.width, range->baseMipLevel), - radv_minify(image->info.height, range->baseMipLevel), + radv_minify(image->vk.extent.width, range->baseMipLevel), + radv_minify(image->vk.extent.height, range->baseMipLevel), }, }, .baseArrayLayer = range->baseArrayLayer, @@ -2219,9 +2219,8 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, range); ++l) { const uint32_t layer_count = image->vk.image_type == VK_IMAGE_TYPE_3D - ? radv_minify(image->info.depth, range->baseMipLevel + l) + ? radv_minify(image->vk.extent.depth, range->baseMipLevel + l) : vk_image_subresource_layer_count(&image->vk, range); - if (cs) { for (uint32_t s = 0; s < layer_count; ++s) { struct radv_meta_blit2d_surf surf; diff --git a/src/amd/vulkan/meta/radv_meta_copy.c b/src/amd/vulkan/meta/radv_meta_copy.c index adfdf59..7672b8f 100644 --- a/src/amd/vulkan/meta/radv_meta_copy.c +++ b/src/amd/vulkan/meta/radv_meta_copy.c @@ -240,8 +240,8 @@ copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf /* RADV_QUEUE_TRANSFER should only be used for the prime blit */ assert(!region->imageOffset.x && !region->imageOffset.y && !region->imageOffset.z); assert(image->vk.image_type == VK_IMAGE_TYPE_2D); - assert(image->info.width == region->imageExtent.width); - assert(image->info.height == region->imageExtent.height); + assert(image->vk.extent.width == region->imageExtent.width); + assert(image->vk.extent.height == region->imageExtent.height); ASSERTED bool res = radv_sdma_copy_image(device, cs, image, buffer, region); assert(res); radv_cs_add_buffer(device->ws, cs, image->bindings[0].bo); @@ -390,9 +390,9 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, if (radv_layout_is_htile_compressed(cmd_buffer->device, dst_image, dst_image_layout, queue_mask) && (region->dstOffset.x || region->dstOffset.y || region->dstOffset.z || - region->extent.width != dst_image->info.width || - region->extent.height != dst_image->info.height || - region->extent.depth != dst_image->info.depth)) { + region->extent.width != dst_image->vk.extent.width || + region->extent.height != dst_image->vk.extent.height || + region->extent.depth != dst_image->vk.extent.depth)) { u_foreach_bit(i, region->dstSubresource.aspectMask) { unsigned aspect_mask = 1u << i; radv_expand_depth_stencil(cmd_buffer, dst_image, diff --git a/src/amd/vulkan/meta/radv_meta_dcc_retile.c b/src/amd/vulkan/meta/radv_meta_dcc_retile.c index 5560dec..a6e05a3 100644 --- a/src/amd/vulkan/meta/radv_meta_dcc_retile.c +++ b/src/amd/vulkan/meta/radv_meta_dcc_retile.c @@ -256,8 +256,8 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image) }, }); - unsigned width = DIV_ROUND_UP(image->info.width, vk_format_get_blockwidth(image->vk.format)); - unsigned height = DIV_ROUND_UP(image->info.height, vk_format_get_blockheight(image->vk.format)); + unsigned width = DIV_ROUND_UP(image->vk.extent.width, vk_format_get_blockwidth(image->vk.format)); + unsigned height = DIV_ROUND_UP(image->vk.extent.height, vk_format_get_blockheight(image->vk.format)); unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width); unsigned dcc_height = diff --git a/src/amd/vulkan/meta/radv_meta_decompress.c b/src/amd/vulkan/meta/radv_meta_decompress.c index f9db95c..f985fea 100644 --- a/src/amd/vulkan/meta/radv_meta_decompress.c +++ b/src/amd/vulkan/meta/radv_meta_decompress.c @@ -402,8 +402,8 @@ radv_process_depth_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i struct radv_image_view iview; uint32_t width, height; - width = radv_minify(image->info.width, range->baseMipLevel + level); - height = radv_minify(image->info.height, range->baseMipLevel + level); + width = radv_minify(image->vk.extent.width, range->baseMipLevel + level); + height = radv_minify(image->vk.extent.height, range->baseMipLevel + level); radv_image_view_init(&iview, device, &(VkImageViewCreateInfo){ @@ -498,8 +498,8 @@ radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l)) continue; - uint32_t width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l); - uint32_t height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l); + uint32_t width = radv_minify(image->vk.extent.width, subresourceRange->baseMipLevel + l); + uint32_t height = radv_minify(image->vk.extent.height, subresourceRange->baseMipLevel + l); radv_CmdSetViewport(cmd_buffer_h, 0, 1, &(VkViewport){.x = 0, @@ -550,8 +550,8 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l)) continue; - width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l); - height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l); + width = radv_minify(image->vk.extent.width, subresourceRange->baseMipLevel + l); + height = radv_minify(image->vk.extent.height, subresourceRange->baseMipLevel + l); for (uint32_t s = 0; s < vk_image_subresource_layer_count(&image->vk, subresourceRange); s++) { radv_image_view_init( diff --git a/src/amd/vulkan/meta/radv_meta_fast_clear.c b/src/amd/vulkan/meta/radv_meta_fast_clear.c index 8fb64e2..d6027bf 100644 --- a/src/amd/vulkan/meta/radv_meta_fast_clear.c +++ b/src/amd/vulkan/meta/radv_meta_fast_clear.c @@ -480,8 +480,8 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i struct radv_image_view iview; uint32_t width, height; - width = radv_minify(image->info.width, range->baseMipLevel + level); - height = radv_minify(image->info.height, range->baseMipLevel + level); + width = radv_minify(image->vk.extent.width, range->baseMipLevel + level); + height = radv_minify(image->vk.extent.height, range->baseMipLevel + level); radv_image_view_init(&iview, device, &(VkImageViewCreateInfo){ @@ -612,8 +612,8 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image * if (op == DCC_DECOMPRESS && !radv_dcc_enabled(image, subresourceRange->baseMipLevel + l)) continue; - width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l); - height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l); + width = radv_minify(image->vk.extent.width, subresourceRange->baseMipLevel + l); + height = radv_minify(image->vk.extent.height, subresourceRange->baseMipLevel + l); radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport){.x = 0, @@ -743,8 +743,8 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag if (!radv_dcc_enabled(image, subresourceRange->baseMipLevel + l)) continue; - width = radv_minify(image->info.width, subresourceRange->baseMipLevel + l); - height = radv_minify(image->info.height, subresourceRange->baseMipLevel + l); + width = radv_minify(image->vk.extent.width, subresourceRange->baseMipLevel + l); + height = radv_minify(image->vk.extent.height, subresourceRange->baseMipLevel + l); for (uint32_t s = 0; s < vk_image_subresource_layer_count(&image->vk, subresourceRange); s++) { radv_image_view_init( diff --git a/src/amd/vulkan/meta/radv_meta_fmask_copy.c b/src/amd/vulkan/meta/radv_meta_fmask_copy.c index 7374427..25782bd 100644 --- a/src/amd/vulkan/meta/radv_meta_fmask_copy.c +++ b/src/amd/vulkan/meta/radv_meta_fmask_copy.c @@ -262,12 +262,12 @@ radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer, /* The region must be a whole image copy. */ if (num_rects != 1 || (rects[0].src_x || rects[0].src_y || rects[0].dst_x || rects[0].dst_y || - rects[0].width != src_image->info.width || rects[0].height != src_image->info.height)) + rects[0].width != src_image->vk.extent.width || rects[0].height != src_image->vk.extent.height)) return false; /* Source/destination images must have identical size. */ - if (src_image->info.width != dst_image->info.width || - src_image->info.height != dst_image->info.height) + if (src_image->vk.extent.width != dst_image->vk.extent.width || + src_image->vk.extent.height != dst_image->vk.extent.height) return false; /* Source/destination images must have identical swizzle. */ @@ -358,7 +358,7 @@ radv_fmask_copy(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf .imageLayout = VK_IMAGE_LAYOUT_GENERAL}, }}}); - radv_unaligned_dispatch(cmd_buffer, src->image->info.width, src->image->info.height, 1); + radv_unaligned_dispatch(cmd_buffer, src->image->vk.extent.width, src->image->vk.extent.height, 1); /* Fixup destination image metadata by copying CMASK/FMASK from the source image. */ radv_fixup_copy_dst_metadata(cmd_buffer, src->image, dst->image); diff --git a/src/amd/vulkan/meta/radv_meta_fmask_expand.c b/src/amd/vulkan/meta/radv_meta_fmask_expand.c index 3b2259c..189b13c 100644 --- a/src/amd/vulkan/meta/radv_meta_fmask_expand.c +++ b/src/amd/vulkan/meta/radv_meta_fmask_expand.c @@ -143,7 +143,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_ .imageLayout = VK_IMAGE_LAYOUT_GENERAL}, }}}); - radv_unaligned_dispatch(cmd_buffer, image->info.width, image->info.height, layer_count); + radv_unaligned_dispatch(cmd_buffer, image->vk.extent.width, image->vk.extent.height, layer_count); radv_image_view_finish(&iview); diff --git a/src/amd/vulkan/meta/radv_meta_resolve.c b/src/amd/vulkan/meta/radv_meta_resolve.c index 4a9d735..0e66d5e 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve.c +++ b/src/amd/vulkan/meta/radv_meta_resolve.c @@ -549,9 +549,9 @@ radv_CmdResolveImage2(VkCommandBuffer commandBuffer, pResolveImageInfo->pRegions[0].dstOffset.y || pResolveImageInfo->pRegions[0].dstOffset.z) resolve_method = RESOLVE_COMPUTE; - if (pResolveImageInfo->pRegions[0].extent.width != src_image->info.width || - pResolveImageInfo->pRegions[0].extent.height != src_image->info.height || - pResolveImageInfo->pRegions[0].extent.depth != src_image->info.depth) + if (pResolveImageInfo->pRegions[0].extent.width != src_image->vk.extent.width || + pResolveImageInfo->pRegions[0].extent.height != src_image->vk.extent.height || + pResolveImageInfo->pRegions[0].extent.depth != src_image->vk.extent.depth) resolve_method = RESOLVE_COMPUTE; } else resolve_method = RESOLVE_COMPUTE; diff --git a/src/amd/vulkan/meta/radv_meta_resolve_cs.c b/src/amd/vulkan/meta/radv_meta_resolve_cs.c index 9debb2a..744486f 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/meta/radv_meta_resolve_cs.c @@ -646,9 +646,9 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_ radv_layout_dcc_compressed(cmd_buffer->device, dst_image, region->dstSubresource.mipLevel, dst_image_layout, queue_mask) && (region->dstOffset.x || region->dstOffset.y || region->dstOffset.z || - region->extent.width != dst_image->info.width || - region->extent.height != dst_image->info.height || - region->extent.depth != dst_image->info.depth)) { + region->extent.width != dst_image->vk.extent.width || + region->extent.height != dst_image->vk.extent.height || + region->extent.depth != dst_image->vk.extent.depth)) { radv_decompress_dcc(cmd_buffer, dst_image, &(VkImageSubresourceRange){ .aspectMask = region->dstSubresource.aspectMask, diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index e41d1bb..4466955 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3565,8 +3565,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) va = radv_buffer_get_va(vrs_image->bindings[0].bo) + vrs_image->bindings[0].offset; va |= vrs_image->planes[0].surface.tile_swizzle << 8; - xmax = vrs_image->info.width - 1; - ymax = vrs_image->info.height - 1; + xmax = vrs_image->vk.extent.width - 1; + ymax = vrs_image->vk.extent.height - 1; } radeon_set_context_reg_seq(cmd_buffer->cs, R_0283F0_PA_SC_VRS_RATE_BASE, 3); @@ -7889,8 +7889,8 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe radv_buffer_init(&htile_buffer, cmd_buffer->device, ds_image->bindings[0].bo, htile_size, htile_offset); - assert(render->area.offset.x + render->area.extent.width <= ds_image->info.width && - render->area.offset.x + render->area.extent.height <= ds_image->info.height); + assert(render->area.offset.x + render->area.extent.width <= ds_image->vk.extent.width && + render->area.offset.x + render->area.extent.height <= ds_image->vk.extent.height); /* Copy the VRS rates to the HTILE buffer. */ radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview->image, &render->area, ds_image, @@ -7903,14 +7903,14 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe */ struct radv_image *ds_image = radv_cmd_buffer_get_vrs_image(cmd_buffer); - if (ds_image && render->area.offset.x < ds_image->info.width && - render->area.offset.y < ds_image->info.height) { + if (ds_image && render->area.offset.x < ds_image->vk.extent.width && + render->area.offset.y < ds_image->vk.extent.height) { /* HTILE buffer */ struct radv_buffer *htile_buffer = cmd_buffer->device->vrs.buffer; VkRect2D area = render->area; - area.extent.width = MIN2(area.extent.width, ds_image->info.width - area.offset.x); - area.extent.height = MIN2(area.extent.height, ds_image->info.height - area.offset.y); + area.extent.width = MIN2(area.extent.width, ds_image->vk.extent.width - area.offset.x); + area.extent.height = MIN2(area.extent.height, ds_image->vk.extent.height - area.offset.y); /* Copy the VRS rates to the HTILE buffer. */ radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview->image, &area, ds_image, diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 8ac2906..f5559ba 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1760,8 +1760,8 @@ radv_initialise_vrs_surface(struct radv_image *image, struct radv_buffer *htile_ S_028038_TILE_SURFACE_ENABLE(1); ds->db_stencil_info = S_02803C_FORMAT(V_028044_STENCIL_INVALID); - ds->db_depth_size = S_02801C_X_MAX(image->info.width - 1) | - S_02801C_Y_MAX(image->info.height - 1); + ds->db_depth_size = S_02801C_X_MAX(image->vk.extent.width - 1) | + S_02801C_Y_MAX(image->vk.extent.height - 1); ds->db_htile_data_base = radv_buffer_get_va(htile_buffer->bo) >> 8; ds->db_htile_surface = S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1) | @@ -1843,8 +1843,8 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf } ds->db_depth_view |= S_028008_MIPID(level); - ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) | - S_02801C_Y_MAX(iview->image->info.height - 1); + ds->db_depth_size = S_02801C_X_MAX(iview->image->vk.extent.width - 1) | + S_02801C_Y_MAX(iview->image->vk.extent.height - 1); if (radv_htile_enabled(iview->image, level)) { ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index dd6984e..49b633f 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -130,7 +130,7 @@ radv_image_use_fast_clear_for_image_early(const struct radv_device *device, if (device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS) return true; - if (image->vk.samples <= 1 && image->info.width * image->info.height <= 512 * 512) { + if (image->vk.samples <= 1 && image->vk.extent.width * image->vk.extent.height <= 512 * 512) { /* Do not enable CMASK or DCC for small surfaces where the cost * of the eliminate pass can be higher than the benefit of fast * clear. RadeonSI does this, but the image threshold is @@ -368,7 +368,7 @@ radv_use_htile_for_image(const struct radv_device *device, const struct radv_ima /* Do not enable HTILE for very small images because it seems less performant but make sure it's * allowed with VRS attachments because we need HTILE on GFX10.3. */ - if (image->info.width * image->info.height < 8 * 8 && + if (image->vk.extent.width * image->vk.extent.height < 8 * 8 && !(device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS) && !(gfx_level == GFX10_3 && device->attachment_vrs_enabled)) return false; @@ -463,8 +463,8 @@ radv_patch_image_dimensions(struct radv_device *device, struct radv_image *image const struct radv_image_create_info *create_info, struct ac_surf_info *image_info) { - unsigned width = image->info.width; - unsigned height = image->info.height; + unsigned width = image->vk.extent.width; + unsigned height = image->vk.extent.height; /* * minigbm sometimes allocates bigger images which is going to result in @@ -486,16 +486,16 @@ radv_patch_image_dimensions(struct radv_device *device, struct radv_image *image } } - if (image->info.width == width && image->info.height == height) + if (image->vk.extent.width == width && image->vk.extent.height == height) return VK_SUCCESS; - if (width < image->info.width || height < image->info.height) { + if (width < image->vk.extent.width || height < image->vk.extent.height) { fprintf(stderr, "The imported image has smaller dimensions than the internal\n" "dimensions. Using it is going to fail badly, so we reject\n" "this import.\n" "(internal dimensions: %d x %d, external dimensions: %d x %d)\n", - image->info.width, image->info.height, width, height); + image->vk.extent.width, image->vk.extent.height, width, height); return VK_ERROR_INVALID_EXTERNAL_HANDLE; } else if (device->physical_device->rad_info.gfx_level >= GFX10) { fprintf(stderr, @@ -503,7 +503,7 @@ radv_patch_image_dimensions(struct radv_device *device, struct radv_image *image "As GFX10 has no separate stride fields we cannot cope with\n" "an inconsistency in width and will fail this import.\n" "(internal dimensions: %d x %d, external dimensions: %d x %d)\n", - image->info.width, image->info.height, width, height); + image->vk.extent.width, image->vk.extent.height, width, height); return VK_ERROR_INVALID_EXTERNAL_HANDLE; } else { fprintf(stderr, @@ -511,7 +511,7 @@ radv_patch_image_dimensions(struct radv_device *device, struct radv_image *image "As GFX10 has no separate stride fields we cannot cope with\n" "an inconsistency and would fail on GFX10.\n" "(internal dimensions: %d x %d, external dimensions: %d x %d)\n", - image->info.width, image->info.height, width, height); + image->vk.extent.width, image->vk.extent.height, width, height); } image_info->width = width; image_info->height = height; @@ -1439,8 +1439,8 @@ radv_query_opaque_metadata(struct radv_device *device, struct radv_image *image, radv_make_texture_descriptor(device, image, false, (VkImageViewType)image->vk.image_type, image->vk.format, &fixedmapping, 0, image->vk.mip_levels - 1, 0, - image->vk.array_layers - 1, image->info.width, image->info.height, - image->info.depth, 0.0f, desc, NULL, 0, NULL, NULL); + image->vk.array_layers - 1, image->vk.extent.width, image->vk.extent.height, + image->vk.extent.depth, 0.0f, desc, NULL, 0, NULL, NULL); si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0, image->planes[0].surface.blk_w, false, false, false, false, @@ -1503,7 +1503,7 @@ radv_image_alloc_single_sample_cmask(const struct radv_device *device, const struct radv_image *image, struct radeon_surf *surf) { if (!surf->cmask_size || surf->cmask_offset || surf->bpe > 8 || image->vk.mip_levels > 1 || - image->info.depth > 1 || radv_image_has_dcc(image) || + image->vk.extent.depth > 1 || radv_image_has_dcc(image) || !radv_image_use_fast_clear_for_image(device, image) || (image->vk.create_flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)) return; @@ -1852,7 +1852,7 @@ radv_image_print_info(struct radv_device *device, struct radv_image *image) " Info: size=%" PRIu64 ", alignment=%" PRIu32 ", " "width=%" PRIu32 ", height=%" PRIu32 ", depth=%" PRIu32 ", " "array_size=%" PRIu32 ", levels=%" PRIu32 "\n", - image->size, image->alignment, image->info.width, image->info.height, image->info.depth, + image->size, image->alignment, image->vk.extent.width, image->vk.extent.height, image->vk.extent.depth, image->vk.array_layers, image->vk.mip_levels); for (unsigned i = 0; i < image->plane_count; ++i) { const struct radv_image_plane *plane = &image->planes[i]; @@ -2207,7 +2207,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, break; case VK_IMAGE_TYPE_3D: assert(range->baseArrayLayer + vk_image_subresource_layer_count(&image->vk, range) - 1 <= - radv_minify(image->info.depth, range->baseMipLevel)); + radv_minify(image->vk.extent.depth, range->baseMipLevel)); break; default: unreachable("bad VkImageType"); @@ -2253,9 +2253,9 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, if (device->physical_device->rad_info.gfx_level >= GFX9) { iview->extent = (VkExtent3D){ - .width = image->info.width, - .height = image->info.height, - .depth = image->info.depth, + .width = image->vk.extent.width, + .height = image->vk.extent.height, + .depth = image->vk.extent.depth, }; } else { iview->extent = iview->vk.extent; @@ -2306,8 +2306,8 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device, iview->extent.width = iview->image->planes[0].surface.u.gfx9.base_mip_width; iview->extent.height = iview->image->planes[0].surface.u.gfx9.base_mip_height; } else { - unsigned lvl_width = radv_minify(image->info.width, range->baseMipLevel); - unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel); + unsigned lvl_width = radv_minify(image->vk.extent.width, range->baseMipLevel); + unsigned lvl_height = radv_minify(image->vk.extent.height, range->baseMipLevel); lvl_width = round_up_u32(lvl_width * view_bw, img_bw); lvl_height = round_up_u32(lvl_height * view_bh, img_bh); @@ -2608,7 +2608,7 @@ radv_GetImageSubresourceLayout(VkDevice _device, VkImage _image, pLayout->depthPitch = surface->u.gfx9.surf_slice_size; pLayout->size = surface->u.gfx9.surf_slice_size; if (image->vk.image_type == VK_IMAGE_TYPE_3D) - pLayout->size *= u_minify(image->info.depth, level); + pLayout->size *= u_minify(image->vk.extent.depth, level); } else { pLayout->offset = (uint64_t)surface->u.legacy.level[level].offset_256B * 256 + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer; @@ -2617,7 +2617,7 @@ radv_GetImageSubresourceLayout(VkDevice _device, VkImage _image, pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4; pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4; if (image->vk.image_type == VK_IMAGE_TYPE_3D) - pLayout->size *= u_minify(image->info.depth, level); + pLayout->size *= u_minify(image->vk.extent.depth, level); } } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 2e90231..3258099 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2906,8 +2906,8 @@ void radv_buffer_view_finish(struct radv_buffer_view *view); static inline bool radv_image_extent_compare(const struct radv_image *image, const VkExtent3D *extent) { - if (extent->width != image->info.width || extent->height != image->info.height || - extent->depth != image->info.depth) + if (extent->width != image->vk.extent.width || extent->height != image->vk.extent.height || + extent->depth != image->vk.extent.depth) return false; return true; } diff --git a/src/amd/vulkan/radv_sdma_copy_image.c b/src/amd/vulkan/radv_sdma_copy_image.c index ae92ede..c94538e 100644 --- a/src/amd/vulkan/radv_sdma_copy_image.c +++ b/src/amd/vulkan/radv_sdma_copy_image.c @@ -36,8 +36,8 @@ radv_sdma_v4_v5_copy_image_to_buffer(struct radv_device *device, struct radeon_c uint64_t dst_address = buffer->bo->va; uint64_t src_address = image->bindings[0].bo->va + image->planes[0].surface.u.gfx9.surf_offset; unsigned src_pitch = image->planes[0].surface.u.gfx9.surf_pitch; - unsigned copy_width = DIV_ROUND_UP(image->info.width, image->planes[0].surface.blk_w); - unsigned copy_height = DIV_ROUND_UP(image->info.height, image->planes[0].surface.blk_h); + unsigned copy_width = DIV_ROUND_UP(image->vk.extent.width, image->planes[0].surface.blk_w); + unsigned copy_height = DIV_ROUND_UP(image->vk.extent.height, image->planes[0].surface.blk_h); bool tmz = false; /* Linear -> linear sub-window copy. */ @@ -187,4 +187,4 @@ radv_sdma_copy_buffer(struct radv_device *device, struct radeon_cmdbuf *cs, uint src_va += csize; size -= csize; } -} \ No newline at end of file +}