From: Ahmed Bougacha Date: Thu, 14 Jul 2016 17:29:46 +0000 (+0000) Subject: [CodeGen] Simplify reg bank/class union is+get into dyn_cast. NFC. X-Git-Tag: llvmorg-3.9.0-rc1~432 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9e511525a0c91cb3f8a5042694864d1372e43c69;p=platform%2Fupstream%2Fllvm.git [CodeGen] Simplify reg bank/class union is+get into dyn_cast. NFC. llvm-svn: 275443 --- diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h index 1b9b337..07d2d01 100644 --- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h @@ -590,9 +590,7 @@ public: /// the select pass, using getRegClass is safe. const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const { const RegClassOrRegBank &Val = VRegInfo[Reg].first; - if (Val.is()) - return Val.get(); - return nullptr; + return Val.dyn_cast(); } /// Return the register bank of \p Reg, or null if Reg has not been assigned @@ -602,9 +600,7 @@ public: /// const RegisterBank *getRegBankOrNull(unsigned Reg) const { const RegClassOrRegBank &Val = VRegInfo[Reg].first; - if (Val.is()) - return Val.get(); - return nullptr; + return Val.dyn_cast(); } /// Return the register bank or register class of \p Reg.