From: Daniel Silsby Date: Wed, 29 Aug 2018 21:32:55 +0000 (+0200) Subject: dmaengine: dma-jz4780: Set DTCn register explicitly X-Git-Tag: v5.4-rc1~2381^2~6^2~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9e4e3a4c00c0af333d1c32925b80d12dc571778b;p=platform%2Fkernel%2Flinux-rpi.git dmaengine: dma-jz4780: Set DTCn register explicitly Normally, we wouldn't set the channel transfer count register directly when using descriptor-driven transfers. However, there is no harm in doing so, and it allows jz4780_dma_desc_residue() to report the correct residue of an ongoing transfer, no matter when it is called. Signed-off-by: Daniel Silsby Signed-off-by: Paul Cercueil Tested-by: Mathieu Malaterre Signed-off-by: Vinod Koul --- diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index d055602..d3b915e 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c @@ -532,6 +532,15 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan) jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT, jzchan->transfer_type); + /* + * Set the transfer count. This is redundant for a descriptor-driven + * transfer. However, there can be a delay between the transfer start + * time and when DTCn reg contains the new transfer count. Setting + * it explicitly ensures residue is computed correctly at all times. + */ + jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC, + jzchan->desc->desc[jzchan->curr_hwdesc].dtc); + /* Write descriptor address and initiate descriptor fetch. */ desc_phys = jzchan->desc->desc_phys + (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));