From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Tue, 10 Oct 2017 11:36:23 +0000 (+0200)
Subject: radv: emit primitive restart from radv_emit_draw_registers()
X-Git-Tag: upstream/18.1.0~4937
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9e45e5c9fdb128e6778c9d59df7fc9bcf5b9339c;p=platform%2Fupstream%2Fmesa.git

radv: emit primitive restart from radv_emit_draw_registers()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a682c5e..33a6832 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1713,33 +1713,6 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
 	assert(cmd_buffer->cs->cdw <= cdw_max);
 }
 
-static void radv_emit_primitive_reset_state(struct radv_cmd_buffer *cmd_buffer,
-					    bool indexed_draw)
-{
-	int32_t primitive_reset_en = indexed_draw && cmd_buffer->state.pipeline->graphics.prim_restart_enable;
-
-	if (primitive_reset_en != cmd_buffer->state.last_primitive_reset_en) {
-		cmd_buffer->state.last_primitive_reset_en = primitive_reset_en;
-		if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
-			radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
-					       primitive_reset_en);
-		} else {
-			radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
-					       primitive_reset_en);
-		}
-	}
-
-	if (primitive_reset_en) {
-		uint32_t primitive_reset_index = cmd_buffer->state.index_type ? 0xffffffffu : 0xffffu;
-
-		if (primitive_reset_index != cmd_buffer->state.last_primitive_reset_index) {
-			cmd_buffer->state.last_primitive_reset_index = primitive_reset_index;
-			radeon_set_context_reg(cmd_buffer->cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
-					       primitive_reset_index);
-		}
-	}
-}
-
 static bool
 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer)
 {
@@ -1801,6 +1774,7 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
 	struct radv_cmd_state *state = &cmd_buffer->state;
 	struct radeon_winsys_cs *cs = cmd_buffer->cs;
 	uint32_t ia_multi_vgt_param;
+	int32_t primitive_reset_en;
 
 	/* Draw state. */
 	ia_multi_vgt_param =
@@ -1822,6 +1796,35 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
 		}
 		state->last_ia_multi_vgt_param = ia_multi_vgt_param;
 	}
+
+	/* Primitive restart. */
+	primitive_reset_en =
+		indexed_draw && state->pipeline->graphics.prim_restart_enable;
+
+	if (primitive_reset_en != state->last_primitive_reset_en) {
+		state->last_primitive_reset_en = primitive_reset_en;
+		if (info->chip_class >= GFX9) {
+			radeon_set_uconfig_reg(cs,
+					       R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
+					       primitive_reset_en);
+		} else {
+			radeon_set_context_reg(cs,
+					       R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
+					       primitive_reset_en);
+		}
+	}
+
+	if (primitive_reset_en) {
+		uint32_t primitive_reset_index =
+			state->index_type ? 0xffffffffu : 0xffffu;
+
+		if (primitive_reset_index != state->last_primitive_reset_index) {
+			radeon_set_context_reg(cs,
+					       R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
+					       primitive_reset_index);
+			state->last_primitive_reset_index = primitive_reset_index;
+		}
+	}
 }
 
 static void
@@ -1859,8 +1862,6 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
 
 	radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
 
-	radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
-
 	radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
 	radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
 			     VK_SHADER_STAGE_ALL_GRAPHICS);