From: Jan Beulich <jbeulich@novell.com>
Date: Wed, 25 Jul 2012 11:34:49 +0000 (+0000)
Subject: MASM accepts ESP/RSP being specified second in a memory address
X-Git-Tag: binutils-2_23-branchpoint~36
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9e2934f7999c248f7e8452d0726541ce9ad9edce;p=platform%2Fupstream%2Fbinutils.git

MASM accepts ESP/RSP being specified second in a memory address
operand, by silently making it the base register despite not being
specified first.

Consequently, we also permit an xmm/ymm index to be specified first
(possibly alone), nevertheless putting it in as index register.

2012-07-24  Jan Beulich <jbeulich@suse.com>

	* config/tc-i386-intel.c (i386_intel_simplify_register): Handle
	xmm/ymm index register being specified first as well as esp/rsp
	base register being specified last in a memory operand.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 445e36d..2d62c41 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,11 @@
 2012-07-24  Jan Beulich <jbeulich@suse.com>
 
+	* config/tc-i386-intel.c (i386_intel_simplify_register): Handle
+	xmm/ymm index register being specified first as well as esp/rsp
+	base register being specified last in a memory operand.
+
+2012-07-24  Jan Beulich <jbeulich@suse.com>
+
 	* config/tc-i386-intel.c (i386_intel_simplify_register):
 	Replace literal 4 by corresponding ESP_REG_NUM.
 
diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c
index 919f27c..099cbfc 100644
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -278,10 +278,24 @@ i386_intel_simplify_register (expressionS *e)
 	}
       i.op[this_operand].regs = i386_regtab + reg_num;
     }
+  else if (!intel_state.index
+	   && (i386_regtab[reg_num].reg_type.bitfield.regxmm
+	       || i386_regtab[reg_num].reg_type.bitfield.regymm))
+    intel_state.index = i386_regtab + reg_num;
   else if (!intel_state.base && !intel_state.in_scale)
     intel_state.base = i386_regtab + reg_num;
   else if (!intel_state.index)
-    intel_state.index = i386_regtab + reg_num;
+    {
+      if (intel_state.in_scale
+	  || i386_regtab[reg_num].reg_type.bitfield.baseindex)
+	intel_state.index = i386_regtab + reg_num;
+      else
+	{
+	  /* Convert base to index and make ESP/RSP the base.  */
+	  intel_state.index = intel_state.base;
+	  intel_state.base = i386_regtab + reg_num;
+	}
+    }
   else
     {
       /* esp is invalid as index */