From: David Daney Date: Tue, 12 May 2009 19:41:54 +0000 (-0700) Subject: MIPS: Remove execution hazard barriers for Octeon. X-Git-Tag: v2.6.31-rc1~291^2~30 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9e290a19f21f4d6c305090d3c61fbfad65908188;p=profile%2Fivi%2Fkernel-adaptation-intel-automotive.git MIPS: Remove execution hazard barriers for Octeon. The Octeon has no execution hazards, so we can remove them and save an instruction per TLB handler invocation. Signed-off-by: David Daney Reviewed by: David VomLehn Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index 04ce6e6..bb291f4 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -47,6 +47,7 @@ #define cpu_has_mips32r2 0 #define cpu_has_mips64r1 0 #define cpu_has_mips64r2 1 +#define cpu_has_mips_r2_exec_hazard 0 #define cpu_has_dsp 0 #define cpu_has_mipsmt 0 #define cpu_has_userlocal 0