From: David Green <david.green@arm.com>
Date: Wed, 27 Jan 2021 09:59:15 +0000 (+0000)
Subject: [ARM] Add neon FP16 scalar_to_vector patterns.
X-Git-Tag: llvmorg-14-init~16832
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=9e2768a3d9285fa3cd8695671a6c132c7fececa8;p=platform%2Fupstream%2Fllvm.git

[ARM] Add neon FP16 scalar_to_vector patterns.

This adds some simple fp16 scalar_to_vector patterns, preventing a
selection failure if this came up.

Differential Revision: https://reviews.llvm.org/D95427
---

diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index a8c0d05d91c4..2872bf055465 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -6482,8 +6482,6 @@ def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
 
 defm : InsertEltF16<f16, v4f16, v8f16>;
 
-//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
-//          (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
           (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
 
@@ -6494,6 +6492,11 @@ def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
           (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
 
+def : Pat<(v4f16 (scalar_to_vector (f16 HPR:$src))),
+          (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), HPR:$src, ssub_0)>;
+def : Pat<(v8f16 (scalar_to_vector (f16 HPR:$src))),
+          (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), HPR:$src, ssub_0)>;
+
 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
           (VSETLNi8  (v8i8  (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
diff --git a/llvm/test/CodeGen/ARM/fp16-insert-extract.ll b/llvm/test/CodeGen/ARM/fp16-insert-extract.ll
index 698df3aa40b3..edd8014cc32e 100644
--- a/llvm/test/CodeGen/ARM/fp16-insert-extract.ll
+++ b/llvm/test/CodeGen/ARM/fp16-insert-extract.ll
@@ -74,6 +74,39 @@ entry:
   ret float %conv
 }
 
+define <4 x half> @insert_v4f16(half %a) {
+; CHECKHARD-LABEL: insert_v4f16:
+; CHECKHARD:       @ %bb.0: @ %entry
+; CHECKHARD-NEXT:    @ kill: def $s0 killed $s0 def $d0
+; CHECKHARD-NEXT:    bx lr
+;
+; CHECKSOFT-LABEL: insert_v4f16:
+; CHECKSOFT:       @ %bb.0: @ %entry
+; CHECKSOFT-NEXT:    vmov.f16 s0, r0
+; CHECKSOFT-NEXT:    vmov r0, r1, d0
+; CHECKSOFT-NEXT:    bx lr
+entry:
+  %res = insertelement <4 x half> undef, half %a, i32 0
+  ret <4 x half> %res
+}
+
+define <8 x half> @insert_v8f16(half %a) {
+; CHECKHARD-LABEL: insert_v8f16:
+; CHECKHARD:       @ %bb.0: @ %entry
+; CHECKHARD-NEXT:    @ kill: def $s0 killed $s0 def $q0
+; CHECKHARD-NEXT:    bx lr
+;
+; CHECKSOFT-LABEL: insert_v8f16:
+; CHECKSOFT:       @ %bb.0: @ %entry
+; CHECKSOFT-NEXT:    vmov.f16 s0, r0
+; CHECKSOFT-NEXT:    vmov r2, r3, d1
+; CHECKSOFT-NEXT:    vmov r0, r1, d0
+; CHECKSOFT-NEXT:    bx lr
+entry:
+  %res = insertelement <8 x half> undef, half %a, i32 0
+  ret <8 x half> %res
+}
+
 define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
 ; CHECKHARD-LABEL: test_vset_lane_f16:
 ; CHECKHARD:       @ %bb.0: @ %entry